SURF
Loading...
Searching...
No Matches
Constants | Instantiations | Procedures | Processes | Records | Signals | Types
AxiStreamDepacketizer2.rtl Architecture Reference
Architecture >> AxiStreamDepacketizer2::rtl

Processes

PROCESS_80  ( axisClk , axisRst )
comb  ( inputAxisMaster , linkGood , outputAxisSlave , r , ramCrcRem , ramPacketActiveOut , ramPacketSeqOut , ramSentEofeOut )
seq  ( axisClk , axisRst )
PROCESS_264  ( axisClk , axisRst )
comb  ( inputAxisMaster , linkGood , outputAxisSlave , r , ramCrcRem , ramPacketActiveOut , ramPacketSeqOut , ramSentEofeOut )
seq  ( axisClk , axisRst )

Procedures

  doTail
  doTail

Constants

CRC_EN_C  boolean := ( CRC_MODE_G/ = " NONE " )
CRC_HEAD_TAIL_C  boolean := ( CRC_MODE_G = " FULL " )
ADDR_WIDTH_C  positive := ite ( ( TDEST_BITS_G = 0 ) , 1 , TDEST_BITS_G )
SEQ_CNT_SIZE_C  positive := ite ( ( SEQ_CNT_SIZE_G = 0 ) , 1 , SEQ_CNT_SIZE_G )
RAM_DATA_WIDTH_C  positive := 32 + 2 + SEQ_CNT_SIZE_C
AXIS_CONFIG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
REG_INIT_C  RegType := ( state = > TERMINATE_S , activeTDest = > ( others = > ' 1 ' ) , packetSeq = > ( others = > ' 0 ' ) , packetActive = > ' 0 ' , sentEofe = > ' 0 ' , ramWe = > ' 0 ' , sideband = > ' 0 ' , crcDataValid = > ' 0 ' , crcDataWidth = > ( others = > ' 1 ' ) , crcInit = > ( others = > ' 1 ' ) , crcReset = > ' 1 ' , linkGoodDly = > ' 0 ' , rdLat = > 2 , debug = > PACKETIZER2_DEBUG_INIT_C , inputAxisSlave = > AXI_STREAM_SLAVE_INIT_C , outputAxisMaster = > ( others = > axiStreamMasterInit ( AXIS_CONFIG_C ) ) )

Types

StateType  ( IDLE_S , WAIT_S , HEADER_S , MOVE_S , TERMINATE_S , CRC_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
inputAxisMaster  AxiStreamMasterType
inputAxisSlave  AxiStreamSlaveType
outputAxisMaster  AxiStreamMasterType
outputAxisSlave  AxiStreamSlaveType
ramDin  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
ramDout  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
ramPacketSeqOut  slv ( SEQ_CNT_SIZE_C- 1 downto 0 )
ramPacketActiveOut  sl
ramSentEofeOut  sl
ramCrcRem  slv ( 31 downto 0 ) := ( others = > ' 1 ' )
ramAddrr  slv ( ADDR_WIDTH_C- 1 downto 0 )
crcIn  slv ( 63 downto 0 ) := ( others = > ' 1 ' )
crcOut  slv ( 31 downto 0 ) := ( others = > ' 1 ' )
crcRem  slv ( 31 downto 0 ) := ( others = > ' 1 ' )

Records

RegType 

Instantiations

u_input  AxiStreamPipeline <Entity AxiStreamPipeline>
u_dualportram_1  DualPortRam <Entity DualPortRam>
u_crc32  Crc32Parallel <Entity Crc32Parallel>
u_crc32  Crc32 <Entity Crc32>
u_output  AxiStreamPipeline <Entity AxiStreamPipeline>
u_input  AxiStreamPipeline <Entity AxiStreamPipeline>
u_dualportram_1  DualPortRam <Entity DualPortRam>
u_crc32  Crc32Parallel <Entity Crc32Parallel>
u_crc32  Crc32 <Entity Crc32>
u_output  AxiStreamPipeline <Entity AxiStreamPipeline>
The documentation for this design unit was generated from the following files: