AxiStreamDeMux Entity Reference

Inheritance diagram for AxiStreamDeMux:

Collaboration diagram for AxiStreamDeMux:

Entities
AxiStreamDeMux.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
ArbiterPkg	Package <ArbiterPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
NUM_MASTERS_G	integer range 1 to 256 := 12
MODE_G	string := " INDEXED "
TDEST_ROUTES_G	slv8Array := ( 0 = > " -------- " )
PIPE_STAGES_G	integer range 0 to 16 := 0
TDEST_HIGH_G	integer range 0 to 7 := 7
TDEST_LOW_G	integer range 0 to 7 := 0

Ports
axisClk	in	sl
axisRst	in	sl
dynamicRouteMasks	in	slv8Array ( NUM_MASTERS_G- 1 downto 0 ) := ( others = > " 00000000 " )
dynamicRouteDests	in	slv8Array ( NUM_MASTERS_G- 1 downto 0 ) := ( others = > " 00000000 " )
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMasters	out	AxiStreamMasterArray ( NUM_MASTERS_G- 1 downto 0 )
mAxisSlaves	in	AxiStreamSlaveArray ( NUM_MASTERS_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamDeMux.vhd
• build/SRC_VHDL/surf/AxiStreamDeMux.vhd