SsiPrbsTx Entity Reference

Inheritance diagram for SsiPrbsTx:

Collaboration diagram for SsiPrbsTx:

Entities
SsiPrbsTx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
AXI_EN_G	sl := ' 1 '
AXI_DEFAULT_PKT_LEN_G	slv ( 31 downto 0 ) := x " 00000FFF "
AXI_DEFAULT_TRIG_DLY_G	slv ( 31 downto 0 ) := x " 00000000 "
VALID_THOLD_G	natural := 1
VALID_BURST_MODE_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
GEN_SYNC_FIFO_G	boolean := false
CASCADE_SIZE_G	positive := 1
FIFO_ADDR_WIDTH_G	positive := 9
FIFO_PAUSE_THRESH_G	positive := 2 ** 8
FIFO_INT_WIDTH_SELECT_G	string := " WIDE "
PRBS_SEED_SIZE_G	natural range 32 to 512 := 32
PRBS_TAPS_G	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
PRBS_INCREMENT_G	boolean := false
MASTER_AXI_STREAM_CONFIG_G	AxiStreamConfigType
MASTER_AXI_PIPE_STAGES_G	natural range 0 to 16 := 0

Ports
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
locClk	in	sl
locRst	in	sl := not RST_POLARITY_G
trig	in	sl := ' 1 '
trigAccept	out	sl
packetLength	in	slv ( 31 downto 0 ) := x " 00000FFF "
forceEofe	in	sl := ' 0 '
busy	out	sl
tDest	in	slv ( 7 downto 0 ) := X " 00 "
tId	in	slv ( 7 downto 0 ) := X " 00 "
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiPrbsTx.vhd
• protocols/ssi/rtl/SsiPrbsTx.vhd