Architecture >> SsiPrbsTx::rtl

Processes
comb	( axilReadMaster , axilWriteMaster , forceEofe , locRst , packetLength , r , tDest , tId , trig , txCtrl , txSlave )
seq	( locClk , locRst )
comb	( axilReadMaster , axilWriteMaster , forceEofe , locRst , packetLength , r , tDest , tId , trig , txCtrl , txSlave )
seq	( locClk , locRst )

Constants
EVENT_CNT_SIZE_C	integer := minimum ( PRBS_SEED_SIZE_G , 32 )
PRBS_BYTES_C	natural := wordCount ( PRBS_SEED_SIZE_G , 8 )
PRBS_SSI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > PRBS_BYTES_C , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > MASTER_AXI_STREAM_CONFIG_G.TKEEP_MODE_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > MASTER_AXI_STREAM_CONFIG_G.TUSER_MODE_C )
TRIG_SRC_AXI_C	sl := ' 0 '
TRIG_SRC_EXT_C	sl := ' 1 '
REG_INIT_C	RegType := ( cntRst = > ' 1 ' , busy = > ' 1 ' , overflow = > ' 0 ' , frameCnt = > ( others = > ' 0 ' ) , length = > ( others = > ' 0 ' ) , packetLength = > AXI_DEFAULT_PKT_LEN_G , dataCnt = > ( others = > ' 0 ' ) , trigDly = > AXI_DEFAULT_TRIG_DLY_G , trigDlyCnt = > ( others = > ' 0 ' ) , eventCnt = > toSlv ( 1 , EVENT_CNT_SIZE_C ) , randomData = > ( others = > ' 0 ' ) , txAxisMaster = > axiStreamMasterInit ( PRBS_SSI_CONFIG_C ) , state = > IDLE_S , axiEn = > AXI_EN_G , trigSrc = > ite ( AXI_EN_G = ' 1 ' , TRIG_SRC_AXI_C , TRIG_SRC_EXT_C ) , oneShot = > ' 0 ' , trig = > ' 0 ' , trigAccept = > ' 0 ' , trigger = > ' 0 ' , cntData = > toSl ( PRBS_INCREMENT_G ) , tDest = > X " 00 " , tId = > X " 00 " , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , SEED_RAND_S , LENGTH_S , DATA_S )

Records
RegType

Instantiations
axistreamfifo_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
axistreamfifo_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

The documentation for this design unit was generated from the following files:

Processes

Constants