AxiAd9467Core.mapping Architecture Reference

Architecture >> AxiAd9467Core::mapping

Signals
status	AxiAd9467StatusType
config	AxiAd9467ConfigType

Instantiations
axiad9467reg_inst	AxiAd9467Reg <Entity AxiAd9467Reg>
axiad9467spi_inst	AxiAd9467Spi <Entity AxiAd9467Spi>
axiad9467pll_inst	AxiAd9467Pll <Entity AxiAd9467Pll>
axiad9467deser_inst	AxiAd9467Deser <Entity AxiAd9467Deser>
axiad9467mon_inst	AxiAd9467Mon <Entity AxiAd9467Mon>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd