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AxiAd9467Spi Entity Reference
Inheritance diagram for AxiAd9467Spi: Collaboration diagram for AxiAd9467Spi:Entities | |
| AxiAd9467Spi.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiAd9467Pkg | Package <AxiAd9467Pkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| AXI_CLK_FREQ_G | real := 125 . 0E + 6 |
Ports | ||
| adcCs | out | sl |
| adcSck | out | sl |
| adcSdio | inout | sl |
| axiClk | in | sl |
| axiRst | in | sl |
| adcSpiIn | in | AxiAd9467SpiInType |
| adcSpiOut | out | AxiAd9467SpiOutType |
The documentation for this design unit was generated from the following file:
- devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd
