AxiAd9467Mon Entity Reference

Inheritance diagram for AxiAd9467Mon:

Entities
AxiAd9467Mon.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
ADC_CLK_FREQ_G	real := 250 . 0E + 6

Ports
adcClk	in	sl
adcRst	in	sl
adcData	in	slv ( 15 downto 0 )
adcDataMon	out	Slv16Array ( 0 to 15 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd