AxiAd9467Mon.rtl Architecture Reference

Architecture >> AxiAd9467Mon::rtl

Processes
comb	( adcData , adcRst , r )
seq	( adcClk )

Constants
MAX_CNT_C	natural := getTimeRatio ( ADC_CLK_FREQ_G , 1 . 0 )
REG_INIT_C	RegType := ( 0 , 0 , ( others = > x " 0000 " ) , IDLE_S )

Types
StateType	( IDLE_S , SMPL_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd