AxiAd9467Core Entity Reference

Inheritance diagram for AxiAd9467Core:

Collaboration diagram for AxiAd9467Core:

Entities
AxiAd9467Core.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiAd9467Pkg	Package <AxiAd9467Pkg>

Generics
TPD_G	time := 1 ns
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32
AXI_CLK_FREQ_G	real := 125 . 0E + 6
ADC_CLK_FREQ_G	real := 250 . 0E + 6
DEMUX_INIT_G	sl := ' 0 '
DELAY_INIT_G	Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
IODELAY_GROUP_G	string := " AXI_AD9467_IODELAY_GRP "

Ports
adcIn	in	AxiAd9467InType
adcInOut	inout	AxiAd9467InOutType
adcOut	out	AxiAd9467OutType
adcClk	in	sl
adcRst	in	sl
adcData	out	slv ( 15 downto 0 )
refClk200Mhz	in	sl
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd