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AxiAd9467Pll Entity Reference
Inheritance diagram for AxiAd9467Pll: Collaboration diagram for AxiAd9467Pll:Entities | |
| AxiAd9467Pll.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| StdRtlPkg | Package <StdRtlPkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| ADC_CLK_FREQ_G | real := 250 . 0E + 6 |
Ports | ||
| adcClkOutP | out | sl |
| adcClkOutN | out | sl |
| adcClkInP | in | sl |
| adcClkInN | in | sl |
| pllLocked | out | sl |
| adcClk | in | sl |
| adcRst | in | sl |
The documentation for this design unit was generated from the following file:
- devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd
