AxiAd9467Pll.mapping Architecture Reference

Architecture >> AxiAd9467Pll::mapping

Constants
ADC_CLK_PERIOD_C	real := 1 . 0 / ADC_CLK_FREQ_G
ADC_CLK_PERIOD_NS_C	real := 1 . 0E + 9 * ADC_CLK_PERIOD_C
CLKFBOUT_MULT_F_C	real := 1 . 0E + 9 / ADC_CLK_FREQ_G

Signals
clkFeedBackIn	sl
clkFeedBack	sl
clkFeedBackOut	sl

Instantiations
ibufgds_inst	ibufgds
mmcme2_adv_inst	mmcme2_adv
bufh_west	bufh
clkoutbufdiff_inst	ClkOutBufDiff <Entity ClkOutBufDiff>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd