AxiAd9467Deser Entity Reference

Inheritance diagram for AxiAd9467Deser:

Collaboration diagram for AxiAd9467Deser:

Entities
AxiAd9467Deser.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiAd9467Pkg	Package <AxiAd9467Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
DELAY_INIT_G	Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
IODELAY_GROUP_G	string := " AXI_AD9467_IODELAY_GRP "

Ports
adcDataOrP	in	sl
adcDataOrN	in	sl
adcDataInP	in	slv ( 7 downto 0 )
adcDataInN	in	slv ( 7 downto 0 )
adcClk	in	sl
adcRst	in	sl
adcData	out	slv ( 15 downto 0 )
refClk200Mhz	in	sl
delayin	in	AxiAd9467DelayInType
delayOut	out	AxiAd9467DelayOutType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd