AxiAd9467Deser.rtl Architecture Reference

Architecture >> AxiAd9467Deser::rtl

Processes
PROCESS_189	( adcClk )

Signals
adcDataPs	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
adcDataNs	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
adcDataP	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
adcDataN	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
adcDataNd	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
adcDmuxA	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
adcDmuxB	slv ( 7 downto 0 ) := ( others = > ' 0 ' )

Attributes
IODELAY_GROUP	string
IODELAY_GROUP	label is IODELAY_GROUP_G

Instantiations
ibufds_or	ibufds
idelayctrl_inst	idelayctrl
axiad9467deserbit_inst	AxiAd9467DeserBit <Entity AxiAd9467DeserBit>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd