SURF  1.0
XauiGthUltraScale.vhd
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1 -------------------------------------------------------------------------------
2 -- File : XauiGthUltraScale.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-04-08
5 -- Last update: 2016-09-29
6 -------------------------------------------------------------------------------
7 -- Description: 10 GigE XAUI for GTH Ultra Scale
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 use work.AxiStreamPkg.all;
23 use work.AxiLitePkg.all;
24 use work.XauiPkg.all;
25 use work.EthMacPkg.all;
26 
27 library unisim;
28 use unisim.vcomponents.all;
29 
30 --! @see entity
31  --! @ingroup ethernet_XauiCore_gthUltraScale
32 entity XauiGthUltraScale is
33  generic (
34  TPD_G : time := 1 ns;
35  -- XAUI Configurations
36  XAUI_20GIGE_G : boolean := false;
37  REF_CLK_FREQ_G : real := 156.25E+6; -- Support 125MHz, 156.25MHz, or 312.5MHz
38  -- AXI-Lite Configurations
39  EN_AXI_REG_G : boolean := false;
40  AXI_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_SLVERR_C;
41  -- AXI Streaming Configurations
42  AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C);
43  port (
44  -- Local Configurations
45  localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C;
46  -- Streaming DMA Interface
47  dmaClk : in sl;
48  dmaRst : in sl;
49  dmaIbMaster : out AxiStreamMasterType;
50  dmaIbSlave : in AxiStreamSlaveType;
51  dmaObMaster : in AxiStreamMasterType;
52  dmaObSlave : out AxiStreamSlaveType;
53  -- Slave AXI-Lite Interface
54  axiLiteClk : in sl := '0';
55  axiLiteRst : in sl := '0';
56  axiLiteReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
57  axiLiteReadSlave : out AxiLiteReadSlaveType;
58  axiLiteWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
59  axiLiteWriteSlave : out AxiLiteWriteSlaveType;
60  -- Misc. Signals
61  extRst : in sl;
62  phyClk : out sl;
63  phyRst : out sl;
64  phyReady : out sl;
65  -- Transceiver Debug Interface
66  gtTxPreCursor : in slv(19 downto 0) := (others => '0');
67  gtTxPostCursor : in slv(19 downto 0) := (others => '0');
68  gtTxDiffCtrl : in slv(15 downto 0) := x"CCCC";
69  gtRxPolarity : in slv(3 downto 0) := x"0";
70  gtTxPolarity : in slv(3 downto 0) := x"0";
71  -- MGT Ports
72  refClk : in sl; -- 125MHz, 156.25MHz, or 312.5MHz
73  gtTxP : out slv(3 downto 0);
74  gtTxN : out slv(3 downto 0);
75  gtRxP : in slv(3 downto 0);
76  gtRxN : in slv(3 downto 0));
77 end XauiGthUltraScale;
78 
79 architecture mapping of XauiGthUltraScale is
80 
81  signal phyRxd : slv(63 downto 0);
82  signal phyRxc : slv(7 downto 0);
83  signal phyTxd : slv(63 downto 0);
84  signal phyTxc : slv(7 downto 0);
85 
86  signal phyClock : sl;
87  signal phyClkBuf : sl;
88  signal phyReset : sl;
89 
90  signal config : XauiConfig;
91  signal status : XauiStatus;
92 
93  signal macRxAxisMaster : AxiStreamMasterType;
94  signal macRxAxisCtrl : AxiStreamCtrlType;
95  signal macTxAxisMaster : AxiStreamMasterType;
96  signal macTxAxisSlave : AxiStreamSlaveType;
97 
98 begin
99 
100  phyClk <= phyClock;
101  phyRst <= phyReset;
102  phyReady <= status.phyReady;
103 
104  --------------------
105  -- Ethernet MAC core
106  --------------------
107  U_MAC : entity work.EthMacTop
108  generic map (
109  TPD_G => TPD_G,
110  PHY_TYPE_G => "XGMII",
111  PRIM_CONFIG_G => AXIS_CONFIG_G)
112  port map (
113  -- Primary Interface
114  primClk => dmaClk,
115  primRst => dmaRst,
116  ibMacPrimMaster => dmaObMaster,
117  ibMacPrimSlave => dmaObSlave,
118  obMacPrimMaster => dmaIbMaster,
119  obMacPrimSlave => dmaIbSlave,
120  -- Ethernet Interface
121  ethClk => phyClock,
122  ethRst => phyReset,
123  ethConfig => config.macConfig,
124  ethStatus => status.macStatus,
125  phyReady => status.phyReady,
126  -- XGMII PHY Interface
127  xgmiiRxd => phyRxd,
128  xgmiiRxc => phyRxc,
129  xgmiiTxd => phyTxd,
130  xgmiiTxc => phyTxc);
131 
132  --------------------
133  -- 10 GigE XAUI Core
134  --------------------
135  GEN_10GIGE : if (XAUI_20GIGE_G = false) generate
136  GEN_125MHz : if (REF_CLK_FREQ_G = 125.00E+6) generate
137  U_XauiGthUltraScaleCore : entity work.XauiGthUltraScale125MHz10GigECore
138  port map (
139  -- Clocks and Resets
140  dclk => phyClock,
141  reset => status.areset,
142  clk156_out => phyClock,
143  clk156_lock => status.clkLock,
144  refclk => refClk,
145  -- PHY Interface
146  xgmii_txd => phyTxd,
147  xgmii_txc => phyTxc,
148  xgmii_rxd => phyRxd,
149  xgmii_rxc => phyRxc,
150  -- MGT Ports
151  xaui_tx_l0_p => gtTxP(0),
152  xaui_tx_l0_n => gtTxN(0),
153  xaui_tx_l1_p => gtTxP(1),
154  xaui_tx_l1_n => gtTxN(1),
155  xaui_tx_l2_p => gtTxP(2),
156  xaui_tx_l2_n => gtTxN(2),
157  xaui_tx_l3_p => gtTxP(3),
158  xaui_tx_l3_n => gtTxN(3),
159  xaui_rx_l0_p => gtRxP(0),
160  xaui_rx_l0_n => gtRxN(0),
161  xaui_rx_l1_p => gtRxP(1),
162  xaui_rx_l1_n => gtRxN(1),
163  xaui_rx_l2_p => gtRxP(2),
164  xaui_rx_l2_n => gtRxN(2),
165  xaui_rx_l3_p => gtRxP(3),
166  xaui_rx_l3_n => gtRxN(3),
167  -- DRP
168  gt0_drpaddr => (others => '0'),
169  gt0_drpen => '0',
170  gt0_drpdi => X"0000",
171  gt0_drpdo => open,
172  gt0_drprdy => open,
173  gt0_drpwe => '0',
174  gt1_drpaddr => (others => '0'),
175  gt1_drpen => '0',
176  gt1_drpdi => X"0000",
177  gt1_drpdo => open,
178  gt1_drprdy => open,
179  gt1_drpwe => '0',
180  gt2_drpaddr => (others => '0'),
181  gt2_drpen => '0',
182  gt2_drpdi => X"0000",
183  gt2_drpdo => open,
184  gt2_drprdy => open,
185  gt2_drpwe => '0',
186  gt3_drpaddr => (others => '0'),
187  gt3_drpen => '0',
188  gt3_drpdi => X"0000",
189  gt3_drpdo => open,
190  gt3_drprdy => open,
191  gt3_drpwe => '0',
192  -- TX Reset and Initialisation
193  gt_txpmareset => B"0000",
194  gt_txpcsreset => B"0000",
195  gt_txresetdone => open,
196  -- RX Reset and Initialisation
197  gt_rxpmareset => B"0000",
198  gt_rxpcsreset => B"0000",
199  gt_rxpmaresetdone => open,
200  gt_rxresetdone => open,
201  -- Clocking
202  gt_rxbufstatus => open,
203  gt_txphaligndone => open,
204  gt_txphinitdone => open,
205  gt_txdlysresetdone => open,
206  gt_qplllock => open,
207  -- Signal Integrity adn Functionality
208  -- Eye Scan
209  gt_eyescantrigger => B"0000",
210  gt_eyescanreset => B"0000",
211  gt_eyescandataerror => open,
212  gt_rxrate => X"000",
213  -- Loopback
214  gt_loopback => X"000",
215  -- Polarity
216  gt_rxpolarity => gtRxPolarity,
217  gt_txpolarity => gtTxPolarity,
218  -- RX Decision Feedback Equalizer (DFE)
219  gt_rxlpmen => B"1111",
220  gt_rxdfelpmreset => B"0000",
221  -- TX Driver
222  gt_txpostcursor => gtTxPostCursor,
223  gt_txprecursor => gtTxPreCursor,
224  gt_txdiffctrl => gtTxDiffCtrl,
225  gt_txinhibit => "0000",
226  -- PRBS
227  gt_rxprbscntreset => B"0000",
228  gt_rxprbserr => open,
229  gt_rxprbssel => X"0000",
230  gt_txprbssel => X"0000",
231  gt_txprbsforceerr => B"0000",
232  gt_rxcdrhold => B"0000",
233  gt_dmonitorout => open,
234  gt_pcsrsvdin => (others => '0'),
235  -- Configuration and Status
236  gt_rxdisperr => open,
237  gt_rxnotintable => open,
238  gt_rxcommadet => open,
239  signal_detect => (others => '1'),
240  debug => status.debugVector,
241  configuration_vector => config.configVector,
242  status_vector => status.statusVector);
243  end generate;
244  GEN_156p25MHz : if (REF_CLK_FREQ_G = 156.25E+6) generate
245  U_XauiGthUltraScaleCore : entity work.XauiGthUltraScale156p25MHz10GigECore
246  port map (
247  -- Clocks and Resets
248  dclk => phyClock,
249  reset => status.areset,
250  clk156_out => phyClock,
251  clk156_lock => status.clkLock,
252  refclk => refClk,
253  -- PHY Interface
254  xgmii_txd => phyTxd,
255  xgmii_txc => phyTxc,
256  xgmii_rxd => phyRxd,
257  xgmii_rxc => phyRxc,
258  -- MGT Ports
259  xaui_tx_l0_p => gtTxP(0),
260  xaui_tx_l0_n => gtTxN(0),
261  xaui_tx_l1_p => gtTxP(1),
262  xaui_tx_l1_n => gtTxN(1),
263  xaui_tx_l2_p => gtTxP(2),
264  xaui_tx_l2_n => gtTxN(2),
265  xaui_tx_l3_p => gtTxP(3),
266  xaui_tx_l3_n => gtTxN(3),
267  xaui_rx_l0_p => gtRxP(0),
268  xaui_rx_l0_n => gtRxN(0),
269  xaui_rx_l1_p => gtRxP(1),
270  xaui_rx_l1_n => gtRxN(1),
271  xaui_rx_l2_p => gtRxP(2),
272  xaui_rx_l2_n => gtRxN(2),
273  xaui_rx_l3_p => gtRxP(3),
274  xaui_rx_l3_n => gtRxN(3),
275  -- DRP
276  gt0_drpaddr => (others => '0'),
277  gt0_drpen => '0',
278  gt0_drpdi => X"0000",
279  gt0_drpdo => open,
280  gt0_drprdy => open,
281  gt0_drpwe => '0',
282  gt1_drpaddr => (others => '0'),
283  gt1_drpen => '0',
284  gt1_drpdi => X"0000",
285  gt1_drpdo => open,
286  gt1_drprdy => open,
287  gt1_drpwe => '0',
288  gt2_drpaddr => (others => '0'),
289  gt2_drpen => '0',
290  gt2_drpdi => X"0000",
291  gt2_drpdo => open,
292  gt2_drprdy => open,
293  gt2_drpwe => '0',
294  gt3_drpaddr => (others => '0'),
295  gt3_drpen => '0',
296  gt3_drpdi => X"0000",
297  gt3_drpdo => open,
298  gt3_drprdy => open,
299  gt3_drpwe => '0',
300  -- TX Reset and Initialisation
301  gt_txpmareset => B"0000",
302  gt_txpcsreset => B"0000",
303  gt_txresetdone => open,
304  -- RX Reset and Initialisation
305  gt_rxpmareset => B"0000",
306  gt_rxpcsreset => B"0000",
307  gt_rxpmaresetdone => open,
308  gt_rxresetdone => open,
309  -- Clocking
310  gt_rxbufstatus => open,
311  gt_txphaligndone => open,
312  gt_txphinitdone => open,
313  gt_txdlysresetdone => open,
314  gt_qplllock => open,
315  -- Signal Integrity adn Functionality
316  -- Eye Scan
317  gt_eyescantrigger => B"0000",
318  gt_eyescanreset => B"0000",
319  gt_eyescandataerror => open,
320  gt_rxrate => X"000",
321  -- Loopback
322  gt_loopback => X"000",
323  -- Polarity
324  gt_rxpolarity => gtRxPolarity,
325  gt_txpolarity => gtTxPolarity,
326  -- RX Decision Feedback Equalizer (DFE)
327  gt_rxlpmen => B"1111",
328  gt_rxdfelpmreset => B"0000",
329  -- TX Driver
330  gt_txpostcursor => gtTxPostCursor,
331  gt_txprecursor => gtTxPreCursor,
332  gt_txdiffctrl => gtTxDiffCtrl,
333  gt_txinhibit => "0000",
334  -- PRBS
335  gt_rxprbscntreset => B"0000",
336  gt_rxprbserr => open,
337  gt_rxprbssel => X"0000",
338  gt_txprbssel => X"0000",
339  gt_txprbsforceerr => B"0000",
340  gt_rxcdrhold => B"0000",
341  gt_dmonitorout => open,
342  gt_pcsrsvdin => (others => '0'),
343  -- Configuration and Status
344  gt_rxdisperr => open,
345  gt_rxnotintable => open,
346  gt_rxcommadet => open,
347  signal_detect => (others => '1'),
348  debug => status.debugVector,
349  configuration_vector => config.configVector,
350  status_vector => status.statusVector);
351  end generate;
352  GEN_312p5MHz : if (REF_CLK_FREQ_G = 312.50E+6) generate
353  U_XauiGthUltraScaleCore : entity work.XauiGthUltraScale312p5MHz10GigECore
354  port map (
355  -- Clocks and Resets
356  dclk => phyClock,
357  reset => status.areset,
358  clk156_out => phyClock,
359  clk156_lock => status.clkLock,
360  refclk => refClk,
361  -- PHY Interface
362  xgmii_txd => phyTxd,
363  xgmii_txc => phyTxc,
364  xgmii_rxd => phyRxd,
365  xgmii_rxc => phyRxc,
366  -- MGT Ports
367  xaui_tx_l0_p => gtTxP(0),
368  xaui_tx_l0_n => gtTxN(0),
369  xaui_tx_l1_p => gtTxP(1),
370  xaui_tx_l1_n => gtTxN(1),
371  xaui_tx_l2_p => gtTxP(2),
372  xaui_tx_l2_n => gtTxN(2),
373  xaui_tx_l3_p => gtTxP(3),
374  xaui_tx_l3_n => gtTxN(3),
375  xaui_rx_l0_p => gtRxP(0),
376  xaui_rx_l0_n => gtRxN(0),
377  xaui_rx_l1_p => gtRxP(1),
378  xaui_rx_l1_n => gtRxN(1),
379  xaui_rx_l2_p => gtRxP(2),
380  xaui_rx_l2_n => gtRxN(2),
381  xaui_rx_l3_p => gtRxP(3),
382  xaui_rx_l3_n => gtRxN(3),
383  -- DRP
384  gt0_drpaddr => (others => '0'),
385  gt0_drpen => '0',
386  gt0_drpdi => X"0000",
387  gt0_drpdo => open,
388  gt0_drprdy => open,
389  gt0_drpwe => '0',
390  gt1_drpaddr => (others => '0'),
391  gt1_drpen => '0',
392  gt1_drpdi => X"0000",
393  gt1_drpdo => open,
394  gt1_drprdy => open,
395  gt1_drpwe => '0',
396  gt2_drpaddr => (others => '0'),
397  gt2_drpen => '0',
398  gt2_drpdi => X"0000",
399  gt2_drpdo => open,
400  gt2_drprdy => open,
401  gt2_drpwe => '0',
402  gt3_drpaddr => (others => '0'),
403  gt3_drpen => '0',
404  gt3_drpdi => X"0000",
405  gt3_drpdo => open,
406  gt3_drprdy => open,
407  gt3_drpwe => '0',
408  -- TX Reset and Initialisation
409  gt_txpmareset => B"0000",
410  gt_txpcsreset => B"0000",
411  gt_txresetdone => open,
412  -- RX Reset and Initialisation
413  gt_rxpmareset => B"0000",
414  gt_rxpcsreset => B"0000",
415  gt_rxpmaresetdone => open,
416  gt_rxresetdone => open,
417  -- Clocking
418  gt_rxbufstatus => open,
419  gt_txphaligndone => open,
420  gt_txphinitdone => open,
421  gt_txdlysresetdone => open,
422  gt_qplllock => open,
423  -- Signal Integrity adn Functionality
424  -- Eye Scan
425  gt_eyescantrigger => B"0000",
426  gt_eyescanreset => B"0000",
427  gt_eyescandataerror => open,
428  gt_rxrate => X"000",
429  -- Loopback
430  gt_loopback => X"000",
431  -- Polarity
432  gt_rxpolarity => gtRxPolarity,
433  gt_txpolarity => gtTxPolarity,
434  -- RX Decision Feedback Equalizer (DFE)
435  gt_rxlpmen => B"1111",
436  gt_rxdfelpmreset => B"0000",
437  -- TX Driver
438  gt_txpostcursor => gtTxPostCursor,
439  gt_txprecursor => gtTxPreCursor,
440  gt_txdiffctrl => gtTxDiffCtrl,
441  gt_txinhibit => "0000",
442  -- PRBS
443  gt_rxprbscntreset => B"0000",
444  gt_rxprbserr => open,
445  gt_rxprbssel => X"0000",
446  gt_txprbssel => X"0000",
447  gt_txprbsforceerr => B"0000",
448  gt_rxcdrhold => B"0000",
449  gt_dmonitorout => open,
450  gt_pcsrsvdin => (others => '0'),
451  -- Configuration and Status
452  gt_rxdisperr => open,
453  gt_rxnotintable => open,
454  gt_rxcommadet => open,
455  signal_detect => (others => '1'),
456  debug => status.debugVector,
457  configuration_vector => config.configVector,
458  status_vector => status.statusVector);
459  end generate;
460  end generate;
461 
462  --------------------
463  -- 20 GigE XAUI Core
464  --------------------
465  GEN_20GIGE : if (XAUI_20GIGE_G = true) generate
466  GEN_125MHz : if (REF_CLK_FREQ_G = 125.00E+6) generate
467  U_XauiGthUltraScaleCore : entity work.XauiGthUltraScale125MHz20GigECore
468  port map (
469  -- Clocks and Resets
470  dclk => phyClock,
471  reset => status.areset,
472  clk156_out => phyClock,
473  clk156_lock => status.clkLock,
474  refclk => refClk,
475  -- PHY Interface
476  xgmii_txd => phyTxd,
477  xgmii_txc => phyTxc,
478  xgmii_rxd => phyRxd,
479  xgmii_rxc => phyRxc,
480  -- MGT Ports
481  xaui_tx_l0_p => gtTxP(0),
482  xaui_tx_l0_n => gtTxN(0),
483  xaui_tx_l1_p => gtTxP(1),
484  xaui_tx_l1_n => gtTxN(1),
485  xaui_tx_l2_p => gtTxP(2),
486  xaui_tx_l2_n => gtTxN(2),
487  xaui_tx_l3_p => gtTxP(3),
488  xaui_tx_l3_n => gtTxN(3),
489  xaui_rx_l0_p => gtRxP(0),
490  xaui_rx_l0_n => gtRxN(0),
491  xaui_rx_l1_p => gtRxP(1),
492  xaui_rx_l1_n => gtRxN(1),
493  xaui_rx_l2_p => gtRxP(2),
494  xaui_rx_l2_n => gtRxN(2),
495  xaui_rx_l3_p => gtRxP(3),
496  xaui_rx_l3_n => gtRxN(3),
497  -- DRP
498  gt0_drpaddr => (others => '0'),
499  gt0_drpen => '0',
500  gt0_drpdi => X"0000",
501  gt0_drpdo => open,
502  gt0_drprdy => open,
503  gt0_drpwe => '0',
504  gt1_drpaddr => (others => '0'),
505  gt1_drpen => '0',
506  gt1_drpdi => X"0000",
507  gt1_drpdo => open,
508  gt1_drprdy => open,
509  gt1_drpwe => '0',
510  gt2_drpaddr => (others => '0'),
511  gt2_drpen => '0',
512  gt2_drpdi => X"0000",
513  gt2_drpdo => open,
514  gt2_drprdy => open,
515  gt2_drpwe => '0',
516  gt3_drpaddr => (others => '0'),
517  gt3_drpen => '0',
518  gt3_drpdi => X"0000",
519  gt3_drpdo => open,
520  gt3_drprdy => open,
521  gt3_drpwe => '0',
522  -- TX Reset and Initialisation
523  gt_txpmareset => B"0000",
524  gt_txpcsreset => B"0000",
525  gt_txresetdone => open,
526  -- RX Reset and Initialisation
527  gt_rxpmareset => B"0000",
528  gt_rxpcsreset => B"0000",
529  gt_rxpmaresetdone => open,
530  gt_rxresetdone => open,
531  -- Clocking
532  gt_rxbufstatus => open,
533  gt_txphaligndone => open,
534  gt_txphinitdone => open,
535  gt_txdlysresetdone => open,
536  gt_qplllock => open,
537  -- Signal Integrity adn Functionality
538  -- Eye Scan
539  gt_eyescantrigger => B"0000",
540  gt_eyescanreset => B"0000",
541  gt_eyescandataerror => open,
542  gt_rxrate => X"000",
543  -- Loopback
544  gt_loopback => X"000",
545  -- Polarity
546  gt_rxpolarity => gtRxPolarity,
547  gt_txpolarity => gtTxPolarity,
548  -- RX Decision Feedback Equalizer (DFE)
549  gt_rxlpmen => B"1111",
550  gt_rxdfelpmreset => B"0000",
551  -- TX Driver
552  gt_txpostcursor => gtTxPostCursor,
553  gt_txprecursor => gtTxPreCursor,
554  gt_txdiffctrl => gtTxDiffCtrl,
555  gt_txinhibit => "0000",
556  -- PRBS
557  gt_rxprbscntreset => B"0000",
558  gt_rxprbserr => open,
559  gt_rxprbssel => X"0000",
560  gt_txprbssel => X"0000",
561  gt_txprbsforceerr => B"0000",
562  gt_rxcdrhold => B"0000",
563  gt_dmonitorout => open,
564  gt_pcsrsvdin => (others => '0'),
565  -- Configuration and Status
566  gt_rxdisperr => open,
567  gt_rxnotintable => open,
568  gt_rxcommadet => open,
569  signal_detect => (others => '1'),
570  debug => status.debugVector,
571  configuration_vector => config.configVector,
572  status_vector => status.statusVector);
573  end generate;
574  GEN_156p25MHz : if (REF_CLK_FREQ_G = 156.25E+6) generate
575  U_XauiGthUltraScaleCore : entity work.XauiGthUltraScale156p25MHz20GigECore
576  port map (
577  -- Clocks and Resets
578  dclk => phyClock,
579  reset => status.areset,
580  clk156_out => phyClock,
581  clk156_lock => status.clkLock,
582  refclk => refClk,
583  -- PHY Interface
584  xgmii_txd => phyTxd,
585  xgmii_txc => phyTxc,
586  xgmii_rxd => phyRxd,
587  xgmii_rxc => phyRxc,
588  -- MGT Ports
589  xaui_tx_l0_p => gtTxP(0),
590  xaui_tx_l0_n => gtTxN(0),
591  xaui_tx_l1_p => gtTxP(1),
592  xaui_tx_l1_n => gtTxN(1),
593  xaui_tx_l2_p => gtTxP(2),
594  xaui_tx_l2_n => gtTxN(2),
595  xaui_tx_l3_p => gtTxP(3),
596  xaui_tx_l3_n => gtTxN(3),
597  xaui_rx_l0_p => gtRxP(0),
598  xaui_rx_l0_n => gtRxN(0),
599  xaui_rx_l1_p => gtRxP(1),
600  xaui_rx_l1_n => gtRxN(1),
601  xaui_rx_l2_p => gtRxP(2),
602  xaui_rx_l2_n => gtRxN(2),
603  xaui_rx_l3_p => gtRxP(3),
604  xaui_rx_l3_n => gtRxN(3),
605  -- DRP
606  gt0_drpaddr => (others => '0'),
607  gt0_drpen => '0',
608  gt0_drpdi => X"0000",
609  gt0_drpdo => open,
610  gt0_drprdy => open,
611  gt0_drpwe => '0',
612  gt1_drpaddr => (others => '0'),
613  gt1_drpen => '0',
614  gt1_drpdi => X"0000",
615  gt1_drpdo => open,
616  gt1_drprdy => open,
617  gt1_drpwe => '0',
618  gt2_drpaddr => (others => '0'),
619  gt2_drpen => '0',
620  gt2_drpdi => X"0000",
621  gt2_drpdo => open,
622  gt2_drprdy => open,
623  gt2_drpwe => '0',
624  gt3_drpaddr => (others => '0'),
625  gt3_drpen => '0',
626  gt3_drpdi => X"0000",
627  gt3_drpdo => open,
628  gt3_drprdy => open,
629  gt3_drpwe => '0',
630  -- TX Reset and Initialisation
631  gt_txpmareset => B"0000",
632  gt_txpcsreset => B"0000",
633  gt_txresetdone => open,
634  -- RX Reset and Initialisation
635  gt_rxpmareset => B"0000",
636  gt_rxpcsreset => B"0000",
637  gt_rxpmaresetdone => open,
638  gt_rxresetdone => open,
639  -- Clocking
640  gt_rxbufstatus => open,
641  gt_txphaligndone => open,
642  gt_txphinitdone => open,
643  gt_txdlysresetdone => open,
644  gt_qplllock => open,
645  -- Signal Integrity adn Functionality
646  -- Eye Scan
647  gt_eyescantrigger => B"0000",
648  gt_eyescanreset => B"0000",
649  gt_eyescandataerror => open,
650  gt_rxrate => X"000",
651  -- Loopback
652  gt_loopback => X"000",
653  -- Polarity
654  gt_rxpolarity => gtRxPolarity,
655  gt_txpolarity => gtTxPolarity,
656  -- RX Decision Feedback Equalizer (DFE)
657  gt_rxlpmen => B"1111",
658  gt_rxdfelpmreset => B"0000",
659  -- TX Driver
660  gt_txpostcursor => gtTxPostCursor,
661  gt_txprecursor => gtTxPreCursor,
662  gt_txdiffctrl => gtTxDiffCtrl,
663  gt_txinhibit => "0000",
664  -- PRBS
665  gt_rxprbscntreset => B"0000",
666  gt_rxprbserr => open,
667  gt_rxprbssel => X"0000",
668  gt_txprbssel => X"0000",
669  gt_txprbsforceerr => B"0000",
670  gt_rxcdrhold => B"0000",
671  gt_dmonitorout => open,
672  gt_pcsrsvdin => (others => '0'),
673  -- Configuration and Status
674  gt_rxdisperr => open,
675  gt_rxnotintable => open,
676  gt_rxcommadet => open,
677  signal_detect => (others => '1'),
678  debug => status.debugVector,
679  configuration_vector => config.configVector,
680  status_vector => status.statusVector);
681  end generate;
682  GEN_312p5MHz : if (REF_CLK_FREQ_G = 312.50E+6) generate
683  U_XauiGthUltraScaleCore : entity work.XauiGthUltraScale312p5MHz20GigECore
684  port map (
685  -- Clocks and Resets
686  dclk => phyClock,
687  reset => status.areset,
688  clk156_out => phyClock,
689  clk156_lock => status.clkLock,
690  refclk => refClk,
691  -- PHY Interface
692  xgmii_txd => phyTxd,
693  xgmii_txc => phyTxc,
694  xgmii_rxd => phyRxd,
695  xgmii_rxc => phyRxc,
696  -- MGT Ports
697  xaui_tx_l0_p => gtTxP(0),
698  xaui_tx_l0_n => gtTxN(0),
699  xaui_tx_l1_p => gtTxP(1),
700  xaui_tx_l1_n => gtTxN(1),
701  xaui_tx_l2_p => gtTxP(2),
702  xaui_tx_l2_n => gtTxN(2),
703  xaui_tx_l3_p => gtTxP(3),
704  xaui_tx_l3_n => gtTxN(3),
705  xaui_rx_l0_p => gtRxP(0),
706  xaui_rx_l0_n => gtRxN(0),
707  xaui_rx_l1_p => gtRxP(1),
708  xaui_rx_l1_n => gtRxN(1),
709  xaui_rx_l2_p => gtRxP(2),
710  xaui_rx_l2_n => gtRxN(2),
711  xaui_rx_l3_p => gtRxP(3),
712  xaui_rx_l3_n => gtRxN(3),
713  -- DRP
714  gt0_drpaddr => (others => '0'),
715  gt0_drpen => '0',
716  gt0_drpdi => X"0000",
717  gt0_drpdo => open,
718  gt0_drprdy => open,
719  gt0_drpwe => '0',
720  gt1_drpaddr => (others => '0'),
721  gt1_drpen => '0',
722  gt1_drpdi => X"0000",
723  gt1_drpdo => open,
724  gt1_drprdy => open,
725  gt1_drpwe => '0',
726  gt2_drpaddr => (others => '0'),
727  gt2_drpen => '0',
728  gt2_drpdi => X"0000",
729  gt2_drpdo => open,
730  gt2_drprdy => open,
731  gt2_drpwe => '0',
732  gt3_drpaddr => (others => '0'),
733  gt3_drpen => '0',
734  gt3_drpdi => X"0000",
735  gt3_drpdo => open,
736  gt3_drprdy => open,
737  gt3_drpwe => '0',
738  -- TX Reset and Initialisation
739  gt_txpmareset => B"0000",
740  gt_txpcsreset => B"0000",
741  gt_txresetdone => open,
742  -- RX Reset and Initialisation
743  gt_rxpmareset => B"0000",
744  gt_rxpcsreset => B"0000",
745  gt_rxpmaresetdone => open,
746  gt_rxresetdone => open,
747  -- Clocking
748  gt_rxbufstatus => open,
749  gt_txphaligndone => open,
750  gt_txphinitdone => open,
751  gt_txdlysresetdone => open,
752  gt_qplllock => open,
753  -- Signal Integrity adn Functionality
754  -- Eye Scan
755  gt_eyescantrigger => B"0000",
756  gt_eyescanreset => B"0000",
757  gt_eyescandataerror => open,
758  gt_rxrate => X"000",
759  -- Loopback
760  gt_loopback => X"000",
761  -- Polarity
762  gt_rxpolarity => gtRxPolarity,
763  gt_txpolarity => gtTxPolarity,
764  -- RX Decision Feedback Equalizer (DFE)
765  gt_rxlpmen => B"1111",
766  gt_rxdfelpmreset => B"0000",
767  -- TX Driver
768  gt_txpostcursor => gtTxPostCursor,
769  gt_txprecursor => gtTxPreCursor,
770  gt_txdiffctrl => gtTxDiffCtrl,
771  gt_txinhibit => "0000",
772  -- PRBS
773  gt_rxprbscntreset => B"0000",
774  gt_rxprbserr => open,
775  gt_rxprbssel => X"0000",
776  gt_txprbssel => X"0000",
777  gt_txprbsforceerr => B"0000",
778  gt_rxcdrhold => B"0000",
779  gt_dmonitorout => open,
780  gt_pcsrsvdin => (others => '0'),
781  -- Configuration and Status
782  gt_rxdisperr => open,
783  gt_rxnotintable => open,
784  gt_rxcommadet => open,
785  signal_detect => (others => '1'),
786  debug => status.debugVector,
787  configuration_vector => config.configVector,
788  status_vector => status.statusVector);
789  end generate;
790  end generate;
791 
792  status.phyReady <= uAnd(status.debugVector);
793 
794  --------------------------
795  -- 10GBASE-R's Reset Logic
796  --------------------------
797  status.areset <= config.softRst or extRst;
798 
799  RstSync_Inst : entity work.RstSync
800  generic map (
801  TPD_G => TPD_G,
802  IN_POLARITY_G => '0',
803  OUT_POLARITY_G => '1',
804  RELEASE_DELAY_G => 4)
805  port map (
806  clk => phyClock,
807  asyncRst => status.clkLock,
808  syncRst => phyReset);
809 
810  --------------------------------
811  -- Configuration/Status Register
812  --------------------------------
813  U_XauiReg : entity work.XauiReg
814  generic map (
815  TPD_G => TPD_G,
816  EN_AXI_REG_G => EN_AXI_REG_G,
817  AXI_ERROR_RESP_G => AXI_ERROR_RESP_G)
818  port map (
819  -- Local Configurations
820  localMac => localMac,
821  -- AXI-Lite Register Interface
822  axiClk => axiLiteClk,
823  axiRst => axiLiteRst,
824  axiReadMaster => axiLiteReadMaster,
825  axiReadSlave => axiLiteReadSlave,
826  axiWriteMaster => axiLiteWriteMaster,
827  axiWriteSlave => axiLiteWriteSlave,
828  -- Configuration and Status Interface
829  phyClk => phyClock,
830  phyRst => phyReset,
831  config => config,
832  status => status);
833 
834 end mapping;
XauiGthUltraScale.axiLiteReadSlave
out axiLiteReadSlaveAxiLiteReadSlaveType
Definition: XauiGthUltraScale.vhd:57
XauiGth7Wrapper.unisim
_library_ unisimunisim
Definition: XauiGth7Wrapper.vhd:26
XauiGthUltraScale.gtTxPostCursor
in gtTxPostCursorslv( 19 downto 0) :=( others => '0')
Definition: XauiGthUltraScale.vhd:67
XauiGthUltraScale.gtTxN
out gtTxNslv( 3 downto 0)
Definition: XauiGthUltraScale.vhd:74
XauiReg.status
in statusXauiStatus
Definition: XauiReg.vhd:48
EthMacTop.primClk
in primClksl
Definition: EthMacTop.vhd:65
RstSync.syncRst
out syncRstsl
Definition: RstSync.vhd:36
XauiGthUltraScale.mapping.macTxAxisSlave
AxiStreamSlaveType macTxAxisSlave
Definition: XauiGthUltraScale.vhd:96
XauiReg.localMac
in localMacslv( 47 downto 0) := MAC_ADDR_INIT_C
Definition: XauiReg.vhd:36
EthMacTop.xgmiiTxd
out xgmiiTxdslv( 63 downto 0)
Definition: EthMacTop.vhd:93
RstSync.IN_POLARITY_G
IN_POLARITY_Gsl := '1'
Definition: RstSync.vhd:28
XauiReg.phyRst
in phyRstsl
Definition: XauiReg.vhd:46
XauiGthUltraScale.dmaIbSlave
in dmaIbSlaveAxiStreamSlaveType
Definition: XauiGthUltraScale.vhd:50
XauiGthUltraScale.gtTxPolarity
in gtTxPolarityslv( 3 downto 0) := x"0"
Definition: XauiGthUltraScale.vhd:70
AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111
XauiReg.axiRst
in axiRstsl
Definition: XauiReg.vhd:39
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
XauiReg.phyClk
in phyClksl
Definition: XauiReg.vhd:45
XauiReg.config
out configXauiConfig
Definition: XauiReg.vhd:47
XauiGthUltraScale.axiLiteWriteSlave
out axiLiteWriteSlaveAxiLiteWriteSlaveType
Definition: XauiGthUltraScale.vhd:59
XauiReg.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_SLVERR_C
Definition: XauiReg.vhd:33
EthMacTop.xgmiiRxc
in xgmiiRxcslv( 7 downto 0) :=( others => '0')
Definition: EthMacTop.vhd:92
XauiGthUltraScale.gtRxP
in gtRxPslv( 3 downto 0)
Definition: XauiGthUltraScale.vhd:75
XauiReg.axiClk
in axiClksl
Definition: XauiReg.vhd:38
EthMacTop.ibMacPrimMaster
in ibMacPrimMasterAxiStreamMasterType
Definition: EthMacTop.vhd:67
XauiPkg.XauiConfig
XauiConfig
Definition: XauiPkg.vhd:31
XauiGthUltraScale.REF_CLK_FREQ_G
REF_CLK_FREQ_Greal := 156.25E+6
Definition: XauiGthUltraScale.vhd:37
EthMacTop.xgmiiTxc
out xgmiiTxcslv( 7 downto 0)
Definition: EthMacTop.vhd:94
XauiGthUltraScale.axiLiteReadMaster
in axiLiteReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: XauiGthUltraScale.vhd:56
XauiGthUltraScale.gtTxP
out gtTxPslv( 3 downto 0)
Definition: XauiGthUltraScale.vhd:73
XauiGthUltraScale.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_SLVERR_C
Definition: XauiGthUltraScale.vhd:40
XauiGthUltraScale.mapping.macRxAxisMaster
AxiStreamMasterType macRxAxisMaster
Definition: XauiGthUltraScale.vhd:93
RstSync.asyncRst
in asyncRstsl
Definition: RstSync.vhd:35
XauiGthUltraScale.EN_AXI_REG_G
EN_AXI_REG_Gboolean := false
Definition: XauiGthUltraScale.vhd:39
EthMacTop.obMacPrimSlave
in obMacPrimSlaveAxiStreamSlaveType
Definition: EthMacTop.vhd:70
XauiReg.axiReadMaster
in axiReadMasterAxiLiteReadMasterType
Definition: XauiReg.vhd:40
RstSync.clk
in clksl
Definition: RstSync.vhd:34
RstSync.OUT_POLARITY_G
OUT_POLARITY_Gsl := '1'
Definition: RstSync.vhd:29
XauiReg.TPD_G
TPD_Gtime := 1 ns
Definition: XauiReg.vhd:31
XauiReg.axiReadSlave
out axiReadSlaveAxiLiteReadSlaveType
Definition: XauiReg.vhd:41
XauiGthUltraScale.axiLiteWriteMaster
in axiLiteWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: XauiGthUltraScale.vhd:58
AxiLitePkg.AXI_RESP_SLVERR_C
slv( 1 downto 0) := "10" AXI_RESP_SLVERR_C
Definition: AxiLitePkg.vhd:36
RstSync.RELEASE_DELAY_G
RELEASE_DELAY_Ginteger range 3 to positive'high:= 3
Definition: RstSync.vhd:31
XauiGth7Wrapper.ieee
_library_ ieeeieee
Definition: XauiGth7Wrapper.vhd:18
XauiGthUltraScale.mapping.macRxAxisCtrl
AxiStreamCtrlType macRxAxisCtrl
Definition: XauiGthUltraScale.vhd:94
EthMacTop.primRst
in primRstsl
Definition: EthMacTop.vhd:66
EthMacTop.obMacPrimMaster
out obMacPrimMasterAxiStreamMasterType
Definition: EthMacTop.vhd:69
EthMacTop.ethRst
in ethRstsl
Definition: EthMacTop.vhd:63
XauiGthUltraScale.gtRxPolarity
in gtRxPolarityslv( 3 downto 0) := x"0"
Definition: XauiGthUltraScale.vhd:69
EthMacTop.xgmiiRxd
in xgmiiRxdslv( 63 downto 0) :=( others => '0')
Definition: EthMacTop.vhd:91
XauiGthUltraScale.gtTxDiffCtrl
in gtTxDiffCtrlslv( 15 downto 0) := x"CCCC"
Definition: XauiGthUltraScale.vhd:68
XauiGthUltraScale.dmaObSlave
out dmaObSlaveAxiStreamSlaveType
Definition: XauiGthUltraScale.vhd:52
XauiGthUltraScale.dmaIbMaster
out dmaIbMasterAxiStreamMasterType
Definition: XauiGthUltraScale.vhd:49
AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59
XauiPkg.debugVector
slv( 5 downto 0) debugVector
Definition: XauiPkg.vhd:47
EthMacTop.ibMacPrimSlave
out ibMacPrimSlaveAxiStreamSlaveType
Definition: EthMacTop.vhd:68
RstSync.TPD_G
TPD_Gtime := 1 ns
Definition: RstSync.vhd:27
XauiPkg.areset
sl areset
Definition: XauiPkg.vhd:44
EthMacTop.ethClk
in ethClksl
Definition: EthMacTop.vhd:62
XauiPkg.XauiStatus
XauiStatus
Definition: XauiPkg.vhd:41
EthMacTop.PRIM_CONFIG_G
PRIM_CONFIG_GAxiStreamConfigType := EMAC_AXIS_CONFIG_C
Definition: EthMacTop.vhd:49
XauiGthUltraScale.localMac
in localMacslv( 47 downto 0) := MAC_ADDR_INIT_C
Definition: XauiGthUltraScale.vhd:45
XauiGthUltraScale.gtTxPreCursor
in gtTxPreCursorslv( 19 downto 0) :=( others => '0')
Definition: XauiGthUltraScale.vhd:66
XauiReg.EN_AXI_REG_G
EN_AXI_REG_Gboolean := false
Definition: XauiReg.vhd:32
EthMacTop.PHY_TYPE_G
PHY_TYPE_Gstring := "XGMII"
Definition: EthMacTop.vhd:36
AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69
AxiStreamPkg.AXI_STREAM_CONFIG_INIT_C
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 16,TDEST_BITS_C => 4,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_NORMAL_C,TUSER_BITS_C => 4,TUSER_MODE_C => TUSER_NORMAL_C) AXI_STREAM_CONFIG_INIT_C
Definition: AxiStreamPkg.vhd:83
XauiPkg.softRst
sl softRst
Definition: XauiPkg.vhd:32
XauiGthUltraScale.mapping.macTxAxisMaster
AxiStreamMasterType macTxAxisMaster
Definition: XauiGthUltraScale.vhd:95
AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85
XauiReg.axiWriteMaster
in axiWriteMasterAxiLiteWriteMasterType
Definition: XauiReg.vhd:42
XauiGthUltraScale.gtRxN
in gtRxNslv( 3 downto 0)
Definition: XauiGthUltraScale.vhd:76
AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125
XauiGthUltraScale.dmaObMaster
in dmaObMasterAxiStreamMasterType
Definition: XauiGthUltraScale.vhd:51
EthMacTop.TPD_G
TPD_Gtime := 1 ns
Definition: EthMacTop.vhd:32
EthMacTop.ethConfig
in ethConfigEthMacConfigType
Definition: EthMacTop.vhd:104
XauiGthUltraScale.AXIS_CONFIG_G
AXIS_CONFIG_GAxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Definition: XauiGthUltraScale.vhd:42
EthMacTop.ethStatus
out ethStatusEthMacStatusType
Definition: EthMacTop.vhd:105
XauiGthUltraScale.XAUI_20GIGE_G
XAUI_20GIGE_Gboolean := false
Definition: XauiGthUltraScale.vhd:36
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
XauiReg.axiWriteSlave
out axiWriteSlaveAxiLiteWriteSlaveType
Definition: XauiReg.vhd:43
EthMacTop.phyReady
in phyReadysl
Definition: EthMacTop.vhd:103