SURF  1.0
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XauiGth7Wrapper Entity Reference
ethernet » XauiCore » gth7
+ Inheritance diagram for XauiGth7Wrapper:
+ Collaboration diagram for XauiGth7Wrapper:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
XauiPkg  Package <XauiPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
USE_GTREFCLK_G  boolean := false
REFCLK_DIV2_G  boolean := false
EN_AXI_REG_G  boolean := false
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
AXIS_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

localMac   in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk   in sl
dmaRst   in sl
dmaIbMaster   out AxiStreamMasterType
dmaIbSlave   in AxiStreamSlaveType
dmaObMaster   in AxiStreamMasterType
dmaObSlave   out AxiStreamSlaveType
axiLiteClk   in sl := ' 0 '
axiLiteRst   in sl := ' 0 '
axiLiteReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave   out AxiLiteReadSlaveType
axiLiteWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave   out AxiLiteWriteSlaveType
extRst   in sl := ' 0 '
phyClk   out sl
phyRst   out sl
phyReady   out sl
gtRefClk   in sl := ' 0 '
gtClkP   in sl := ' 1 '
gtClkN   in sl := ' 0 '
gtTxP   out slv ( 3 downto 0 )
gtTxN   out slv ( 3 downto 0 )
gtRxP   in slv ( 3 downto 0 )
gtRxN   in slv ( 3 downto 0 )

Detailed Description

See also
entity

Definition at line 31 of file XauiGth7Wrapper.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file XauiGth7Wrapper.vhd.

◆ USE_GTREFCLK_G

USE_GTREFCLK_G boolean := false
Generic

Definition at line 35 of file XauiGth7Wrapper.vhd.

◆ REFCLK_DIV2_G

REFCLK_DIV2_G boolean := false
Generic

Definition at line 36 of file XauiGth7Wrapper.vhd.

◆ EN_AXI_REG_G

EN_AXI_REG_G boolean := false
Generic

Definition at line 38 of file XauiGth7Wrapper.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 39 of file XauiGth7Wrapper.vhd.

◆ AXIS_CONFIG_G

AXIS_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 41 of file XauiGth7Wrapper.vhd.

◆ localMac

localMac in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
Port

Definition at line 44 of file XauiGth7Wrapper.vhd.

◆ dmaClk

dmaClk in sl
Port

Definition at line 46 of file XauiGth7Wrapper.vhd.

◆ dmaRst

dmaRst in sl
Port

Definition at line 47 of file XauiGth7Wrapper.vhd.

◆ dmaIbMaster

dmaIbMaster out AxiStreamMasterType
Port

Definition at line 48 of file XauiGth7Wrapper.vhd.

◆ dmaIbSlave

dmaIbSlave in AxiStreamSlaveType
Port

Definition at line 49 of file XauiGth7Wrapper.vhd.

◆ dmaObMaster

dmaObMaster in AxiStreamMasterType
Port

Definition at line 50 of file XauiGth7Wrapper.vhd.

◆ dmaObSlave

dmaObSlave out AxiStreamSlaveType
Port

Definition at line 51 of file XauiGth7Wrapper.vhd.

◆ axiLiteClk

axiLiteClk in sl := ' 0 '
Port

Definition at line 53 of file XauiGth7Wrapper.vhd.

◆ axiLiteRst

axiLiteRst in sl := ' 0 '
Port

Definition at line 54 of file XauiGth7Wrapper.vhd.

◆ axiLiteReadMaster

axiLiteReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 55 of file XauiGth7Wrapper.vhd.

◆ axiLiteReadSlave

axiLiteReadSlave out AxiLiteReadSlaveType
Port

Definition at line 56 of file XauiGth7Wrapper.vhd.

◆ axiLiteWriteMaster

axiLiteWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 57 of file XauiGth7Wrapper.vhd.

◆ axiLiteWriteSlave

axiLiteWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 58 of file XauiGth7Wrapper.vhd.

◆ extRst

extRst in sl := ' 0 '
Port

Definition at line 60 of file XauiGth7Wrapper.vhd.

◆ phyClk

phyClk out sl
Port

Definition at line 61 of file XauiGth7Wrapper.vhd.

◆ phyRst

phyRst out sl
Port

Definition at line 62 of file XauiGth7Wrapper.vhd.

◆ phyReady

phyReady out sl
Port

Definition at line 63 of file XauiGth7Wrapper.vhd.

◆ gtRefClk

gtRefClk in sl := ' 0 '
Port

Definition at line 65 of file XauiGth7Wrapper.vhd.

◆ gtClkP

gtClkP in sl := ' 1 '
Port

Definition at line 66 of file XauiGth7Wrapper.vhd.

◆ gtClkN

gtClkN in sl := ' 0 '
Port

Definition at line 67 of file XauiGth7Wrapper.vhd.

◆ gtTxP

gtTxP out slv ( 3 downto 0 )
Port

Definition at line 69 of file XauiGth7Wrapper.vhd.

◆ gtTxN

gtTxN out slv ( 3 downto 0 )
Port

Definition at line 70 of file XauiGth7Wrapper.vhd.

◆ gtRxP

gtRxP in slv ( 3 downto 0 )
Port

Definition at line 71 of file XauiGth7Wrapper.vhd.

◆ gtRxN

gtRxN in slv ( 3 downto 0 )
Port

Definition at line 72 of file XauiGth7Wrapper.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file XauiGth7Wrapper.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file XauiGth7Wrapper.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file XauiGth7Wrapper.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 22 of file XauiGth7Wrapper.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file XauiGth7Wrapper.vhd.

◆ XauiPkg

XauiPkg
Package

Definition at line 24 of file XauiGth7Wrapper.vhd.

◆ unisim

unisim
Library

Definition at line 26 of file XauiGth7Wrapper.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 27 of file XauiGth7Wrapper.vhd.

The documentation for this class was generated from the following file: