Architecture >> fifo_tb::fifo_tb

Constants
SRC_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 2 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
FIFO_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 4 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
EP_COUNT_C	integer := 4
TPD_C	time := 1 ns

Signals
axiClk	sl
axiClkRst	sl
prbsMaster	AxiStreamMasterArray ( EP_COUNT_C- 1 downto 0 )
prbsSlave	AxiStreamSlaveArray ( EP_COUNT_C- 1 downto 0 )
wideMaster	AxiStreamMasterArray ( EP_COUNT_C- 1 downto 0 )
wideSlave	AxiStreamSlaveArray ( EP_COUNT_C- 1 downto 0 )
muxMaster	AxiStreamMasterType
muxSlave	AxiStreamSlaveType
fifoMaster	AxiStreamMasterType
fifoSlave	AxiStreamSlaveType
demuxMaster	AxiStreamMasterArray ( EP_COUNT_C- 1 downto 0 )
demuxSlave	AxiStreamSlaveArray ( EP_COUNT_C- 1 downto 0 )
updated	slv ( EP_COUNT_C- 1 downto 0 )
errorDet	slv ( EP_COUNT_C- 1 downto 0 )

Instantiations
prbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_axistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_mux	AxiStreamMux <Entity AxiStreamMux>
u_axistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_demux	AxiStreamDeMux <Entity AxiStreamDeMux>
ssiprbsrx_inst	SsiPrbsRx <Entity SsiPrbsRx>
prbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_axistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_mux	AxiStreamMux <Entity AxiStreamMux>
u_axistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_demux	AxiStreamDeMux <Entity AxiStreamDeMux>
ssiprbsrx_inst	SsiPrbsRx <Entity SsiPrbsRx>

The documentation for this design unit was generated from the following files:

Processes

Constants