Architecture >> SrpV3AxiWrapper::rtl

Constants
FSM_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
SRP_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
AXI_CONFIG_C	AxiConfigType := ( ADDR_WIDTH_C = > 12 , DATA_BYTES_C = > 8 , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )
TPD_C	time := 10 ns/ 4

Signals
axisRst	sl := ' 0 '
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
sAxisMaster32	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave32	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
srpIbMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srpIbSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
srpObMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srpObSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mAxisMaster32	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave32	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_mem	AxiRam <Entity AxiRam>
u_srpv3	SrpV3Axi <Entity SrpV3Axi>
u_txresize	AxiStreamResize <Entity AxiStreamResize>
u_rxresize	AxiStreamResize <Entity AxiStreamResize>

The documentation for this design unit was generated from the following file:

Constants

Signals