SrpV3Axi Entity Reference

Inheritance diagram for SrpV3Axi:

Collaboration diagram for SrpV3Axi:

Entities
SrpV3Axi.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
SrpV3Pkg	Package <SrpV3Pkg>

Generics
TPD_G	time := 1 ns
PIPE_STAGES_G	natural range 0 to 16 := 0
FIFO_PAUSE_THRESH_G	positive range 1 to 511 := 256
TX_VALID_THOLD_G	positive := 1
SLAVE_READY_EN_G	boolean := true
GEN_SYNC_FIFO_G	boolean := false
AXI_CLK_FREQ_G	real := 156 . 25E + 6
AXI_CONFIG_G	AxiConfigType
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 1111 "
ACK_WAIT_BVALID_G	boolean := true
AXI_STREAM_CONFIG_G	AxiStreamConfigType
UNALIGNED_ACCESS_G	boolean := false
BYTE_ACCESS_G	boolean := false
WRITE_EN_G	boolean := true
READ_EN_G	boolean := true

Ports
sAxisClk	in	sl
sAxisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axiClk	in	sl
axiRst	in	sl
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SrpV3Axi.vhd
• protocols/srp/rtl/SrpV3Axi.vhd