SrpV3Axi.rtl Architecture Reference

Architecture >> SrpV3Axi::rtl

Processes
comb	( axiRst , r , rdDmaAck , srpReq , wrDmaAck )
seq	( axiClk )
comb	( axiRst , r , rdDmaAck , srpReq , wrDmaAck )
seq	( axiClk )

Constants
DMA_AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > AXI_STREAM_CONFIG_G.TSTRB_EN_C , TDATA_BYTES_C = > AXI_CONFIG_G.DATA_BYTES_C , TDEST_BITS_C = > AXI_STREAM_CONFIG_G.TDEST_BITS_C , TID_BITS_C = > AXI_STREAM_CONFIG_G.TID_BITS_C , TKEEP_MODE_C = > AXI_STREAM_CONFIG_G.TKEEP_MODE_C , TUSER_BITS_C = > AXI_STREAM_CONFIG_G.TUSER_BITS_C , TUSER_MODE_C = > AXI_STREAM_CONFIG_G.TUSER_MODE_C )
REG_INIT_C	RegType := ( srpAck = > SRPV3_ACK_INIT_C , wrDmaReq = > AXI_WRITE_DMA_REQ_INIT_C , rdDmaReq = > AXI_READ_DMA_REQ_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
srpReq	SrpV3ReqType
wrDmaAck	AxiWriteDmaAckType
rdDmaAck	AxiReadDmaAckType
srpWrMaster	AxiStreamMasterType
srpWrSlave	AxiStreamSlaveType
srpRdMaster	AxiStreamMasterType
srpRdSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_srpv3core_1	SrpV3Core <Entity SrpV3Core>
u_axistreamdmawrite_1	AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_axistreamdmaread_1	AxiStreamDmaRead <Entity AxiStreamDmaRead>
u_srpv3core_1	SrpV3Core <Entity SrpV3Core>
u_axistreamdmawrite_1	AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_axistreamdmaread_1	AxiStreamDmaRead <Entity AxiStreamDmaRead>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SrpV3Axi.vhd
• protocols/srp/rtl/SrpV3Axi.vhd