AxiRam Entity Reference

Inheritance diagram for AxiRam:

Collaboration diagram for AxiRam:

Entities
AxiRam.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
READ_LATENCY_G	natural range 0 to 2 := 2
AXI_CONFIG_G	AxiConfigType

Ports
axiClk	in	sl
axiRst	in	sl
sAxiWriteMaster	in	AxiWriteMasterType
sAxiWriteSlave	out	AxiWriteSlaveType
sAxiReadMaster	in	AxiReadMasterType
sAxiReadSlave	out	AxiReadSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiRam.vhd
• build/SRC_VHDL/surf/AxiRam.vhd