AxiRam.structure Architecture Reference

Architecture >> AxiRam::structure

Processes
comb	( axiRst , r , rdData , sAxiReadMaster , sAxiWriteMaster )
seq	( axiClk )
comb	( axiRst , r , rdData , sAxiReadMaster , sAxiWriteMaster )
seq	( axiClk )

Constants
DATA_BYTES_C	positive := AXI_CONFIG_G.DATA_BYTES_C
DATA_WIDTH_C	positive := 8 * DATA_BYTES_C
OFFSET_C	positive := ite ( DATA_BYTES_C = 1 , 0 , log2 ( DATA_BYTES_C ) )
ADDR_WIDTH_C	positive := AXI_CONFIG_G.ADDR_WIDTH_C- OFFSET_C
REG_INIT_C	RegType := ( wrData = > ( others = > ' 0 ' ) , wrAddr = > ( others = > ' 0 ' ) , wstrb = > ( others = > ' 0 ' ) , wid = > ( others = > ' 0 ' ) , awlen = > ( others = > ' 0 ' ) , sAxiWriteSlave = > AXI_WRITE_SLAVE_INIT_C , wrState = > WR_ADDR_S , rdAddr = > ( others = > ' 0 ' ) , rid = > ( others = > ' 0 ' ) , arlen = > ( others = > ' 0 ' ) , sAxiReadSlave = > AXI_READ_SLAVE_INIT_C , rdEn = > ( others = > ' 0 ' ) , rdLat = > ( others = > ' 0 ' ) , rdState = > RD_ADDR_S )

Types
WrStateType	( WR_ADDR_S , WR_DATA_S , WR_BLOWOFF_S )
RdStateType	( RD_ADDR_S , RD_PIPELINE_S , RD_DATA_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
wrEn	sl
wrData	slv ( DATA_WIDTH_C- 1 downto 0 )
wrAddr	slv ( ADDR_WIDTH_C- 1 downto 0 )
wstrb	slv ( DATA_BYTES_C- 1 downto 0 )
rdEn	slv ( 1 downto 0 )
rdData	slv ( DATA_WIDTH_C- 1 downto 0 )
rdAddr	slv ( ADDR_WIDTH_C- 1 downto 0 )

Records
RegType

Instantiations
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>

---

The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiRam.vhd
• build/SRC_VHDL/surf/AxiRam.vhd