Architecture >> RoCEv2AxiStreamRdma::rtl

Constants
NUM_AXIL_MASTERS_C	positive := 3
XBAR_ENGINE_C	natural := 0
XBAR_DCQCN_C	natural := 1
XBAR_RDMA_C	natural := 2
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 16 , 12 )

Signals
axilWriteMastersX	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilWriteSlavesX	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C )
axilReadMastersX	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadSlavesX	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C )
ibUdpMasterRoce	AxiStreamMasterType
ibUdpSlaveRoce	AxiStreamSlaveType
cnpReceived	sl
dmaReadReqMaster	RoCEv2DmaReadReqMasterType := ROCE_DMA_READ_REQ_MASTER_INIT_C
dmaReadReqSlave	RoCEv2DmaReadReqSlaveType := ROCE_DMA_READ_REQ_SLAVE_INIT_C
dmaReadRespMaster	RoCEv2DmaReadRespMasterType := ROCE_DMA_READ_RESP_MASTER_INIT_C
dmaReadRespSlave	RoCEv2DmaReadRespSlaveType := ROCE_DMA_READ_RESP_SLAVE_INIT_C
workReqMaster	RoCEv2WorkReqMasterType := ROCE_WORK_REQ_MASTER_INIT_C
workReqSlave	RoCEv2WorkReqSlaveType := ROCE_WORK_REQ_SLAVE_INIT_C
workCompMaster	RoCEv2WorkCompMasterType := ROCE_WORK_COMP_MASTER_INIT_C
workCompSlave	RoCEv2WorkCompSlaveType := ROCE_WORK_COMP_SLAVE_INIT_C

Instantiations
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_roceengine	RoCEv2Engine <Entity RoCEv2Engine>
u_dcqcn	RoCEv2Dcqcn <Entity RoCEv2Dcqcn>
u_core	RoCEv2AxiStreamRdmaCore <Entity RoCEv2AxiStreamRdmaCore>

The documentation for this design unit was generated from the following file:

Constants

Signals