RoCEv2AxiStreamRdma Entity Reference

Inheritance diagram for RoCEv2AxiStreamRdma:

Collaboration diagram for RoCEv2AxiStreamRdma:

Entities
RoCEv2AxiStreamRdma.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
RoCEv2Pkg	Package <RoCEv2Pkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
DCQCN_EN_G	boolean := true
AXIL_BASE_ADDR_G	slv ( 31 downto 0 )
AXIS_CONFIG_G	AxiStreamConfigType
RING_SLOTS_G	positive := 16
ROCE_CLK_FREQ_G	real := 156 . 25E + 6
DISPATCH_COUNTER_BITS_G	positive := 24

Ports
roceClk	in	sl
roceRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
obUdpMaster	in	AxiStreamMasterType
obUdpSlave	out	AxiStreamSlaveType
ibUdpMaster	out	AxiStreamMasterType
ibUdpSlave	in	AxiStreamSlaveType
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2AxiStreamRdma.vhd