RoCEv2Dcqcn Entity Reference

Inheritance diagram for RoCEv2Dcqcn:

Collaboration diagram for RoCEv2Dcqcn:

Entities
RoCEv2Dcqcn.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
LINE_RATE_G	integer := 1_250_000_000
CLK_FREQ_G	real := 156 . 25E + 6
AXIS_CONFIG_G	AxiStreamConfigType := SSI_CONFIG_INIT_C
RST_ASYNC_G	boolean := false
RST_POLARITY_G	sl := ' 1 '

Ports
axisClk	in	sl
axisRst	in	sl
cnp	in	sl
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2Dcqcn.vhd