RoCEv2Dcqcn.rtl Architecture Reference

Architecture >> RoCEv2Dcqcn::rtl

Processes
comb	( alphaValid , axilReadMaster , axilWriteMaster , axisRst , cnpCnt , cnpRe , decValid , incValid , newAlpha , newDecRc , newDecRt , newIncRc , newIncRt , r )
seq	( axisClk , axisRst )

Constants
CNP_COUNTER_BITS_C	positive range 1 to 20 := 16
CLK_PERIOD_C	real := 1 . 0 / CLK_FREQ_G
LINE_RATE_SLV_C	slv ( 31 downto 0 ) := conv_std_logic_vector ( LINE_RATE_G , 32 )
RATE_INC_INTERVAL_INIT_C	real := 1 . 5E - 3
RATE_DEC_INTERVAL_INIT_C	real := 4 . 0E - 6
ALPHA_UPD_INTERVAL_INIT_C	real := 55 . 0E - 6
RATE_INC_INTERVAL_CLK_CYCLES_INIT_C	slv ( 31 downto 0 ) := toSlv ( getTimeRatio ( RATE_INC_INTERVAL_INIT_C , CLK_PERIOD_C ) , 32 )
RATE_DEC_INTERVAL_CLK_CYCLES_INIT_C	slv ( 15 downto 0 ) := toSlv ( getTimeRatio ( RATE_DEC_INTERVAL_INIT_C , CLK_PERIOD_C ) , 16 )
ALPHA_UPD_INTERVAL_CLK_CYCLES_INIT_C	slv ( 15 downto 0 ) := toSlv ( getTimeRatio ( ALPHA_UPD_INTERVAL_INIT_C , CLK_PERIOD_C ) , 16 )
REG_INIT_C	RegType := ( Rc = > LINE_RATE_SLV_C , Rt = > LINE_RATE_SLV_C , alpha = > ( others = > ' 1 ' ) , alphaG = > " 1111111100 " , dec_gain = > x " 1 " , Rai = > x " 005B8D80 " , Rhai = > x " 00B71B00 " , clampTgtRate = > ' 0 ' , dcqcnBypass = > ' 0 ' , Rmin = > x " 00989680 " , cnpDecDetected = > ' 0 ' , cnpAlphaDetected = > ' 0 ' , cnpCnt = > ( others = > ' 0 ' ) , cnpCntRst = > ' 0 ' , incReset = > ' 0 ' , incEn = > ' 0 ' , decEn = > ' 0 ' , alphaUpdEn = > ' 0 ' , rateIncInterval = > RATE_INC_INTERVAL_CLK_CYCLES_INIT_C , rateDecInterval = > RATE_DEC_INTERVAL_CLK_CYCLES_INIT_C , alphaUpdInterval = > ALPHA_UPD_INTERVAL_CLK_CYCLES_INIT_C , timeStageThreshold = > x " 05 " , firstCnp = > true , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , THE_CNP_AFTERMATH_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
timeStage	slv ( 7 downto 0 )
cnpRe	sl
newDecRc	slv ( 31 downto 0 )
newDecRt	slv ( 31 downto 0 )
newIncRc	slv ( 31 downto 0 )
newIncRt	slv ( 31 downto 0 )
newAlpha	slv ( 9 downto 0 )
decValid	sl
incValid	sl
alphaValid	sl
cnpCnt	slv ( CNP_COUNTER_BITS_C- 1 downto 0 )
cnpCntRst	sl

Records
RegType

Instantiations
cnpedge_1	SynchronizerEdge <Entity SynchronizerEdge>
synchronizeroneshotcnt_1	SynchronizerOneShotCnt <Entity SynchronizerOneShotCnt>
ratedecproc_1	RoCEv2RateDecProc <Entity RoCEv2RateDecProc>
rateincproc_1	RoCEv2RateIncProc <Entity RoCEv2RateIncProc>
alphaupdate_1	RoCEv2AlphaUpdate <Entity RoCEv2AlphaUpdate>
tokenbucket_1	RoCEv2TokenBucket <Entity RoCEv2TokenBucket>

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2Dcqcn.vhd