RoCEv2RateDecProc Entity Reference

Inheritance diagram for RoCEv2RateDecProc:

Entities
RoCEv2RateDecProc.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
RST_POLARITY_G	sl := ' 1 '

Ports
clk	in	sl
rst	in	sl
start	in	sl
cnpDetected	in	sl
clampTgtRate	in	sl
alpha	in	slv ( 9 downto 0 )
dec_gain	in	slv ( 3 downto 0 )
Rmin	in	slv ( 31 downto 0 )
rateDecInterval	in	slv ( 15 downto 0 )
timeStage	in	slv ( 7 downto 0 )
curRc	in	slv ( 31 downto 0 )
curRt	in	slv ( 31 downto 0 )
newRc	out	slv ( 31 downto 0 )
newRt	out	slv ( 31 downto 0 )
valid	out	sl

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2RateDecProc.vhd