RoCEv2RateDecProc.rtl Architecture Reference

Architecture >> RoCEv2RateDecProc::rtl

Processes
comb	( Rmin , alpha , clampTgtRate , cnpDetected , curRc , curRt , dec_gain , r , rateDecInterval , rst , start , timeStage )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( timer = > ( others = > ' 0 ' ) , newRc = > ( others = > ' 0 ' ) , newRt = > ( others = > ' 0 ' ) , doUpdate = > ' 0 ' , mult = > ( others = > ' 0 ' ) , shift_val = > 0 , valid = > ' 0 ' , state = > IDLE_S )

Types
StateType	( IDLE_S , COUNTING_S , UPDATE1_S , UPDATE2_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2RateDecProc.vhd