RoCEv2RateIncProc Entity Reference

Inheritance diagram for RoCEv2RateIncProc:

Entities
RoCEv2RateIncProc.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
LINE_RATE_G	integer := 1_250_000_000
RST_ASYNC_G	boolean := false
RST_POLARITY_G	sl := ' 1 '

Ports
clk	in	sl
rst	in	sl
start	in	sl
rstTimers	in	sl
rateIncInterval	in	slv ( 31 downto 0 )
Rai	in	slv ( 31 downto 0 )
Rhai	in	slv ( 31 downto 0 )
curRc	in	slv ( 31 downto 0 )
curRt	in	slv ( 31 downto 0 )
timeStageThreshold	in	slv ( 7 downto 0 )
timeStage	out	slv ( 7 downto 0 )
newRc	out	slv ( 31 downto 0 )
newRt	out	slv ( 31 downto 0 )
valid	out	sl

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2RateIncProc.vhd