RoCEv2RateIncProc.rtl Architecture Reference

Architecture >> RoCEv2RateIncProc::rtl

Processes
comb	( Rai , Rhai , curRc , curRt , r , rateIncInterval , rst , rstTimers , start , timeStageThreshold )
seq	( clk , rst )

Constants
LINE_RATE_SLV_C	slv ( 31 downto 0 ) := toSlv ( LINE_RATE_G , 32 )
REG_INIT_C	RegType := ( timer = > ( others = > ' 0 ' ) , timeStage = > ( others = > ' 0 ' ) , newRc = > ( others = > ' 0 ' ) , newRt = > ( others = > ' 0 ' ) , valid = > ' 0 ' , state = > IDLE_S )

Types
StateType	( IDLE_S , COUNTING_S , FAST_REC_S , ADDITIVE_INC_S , HYPER_INC_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2RateIncProc.vhd