RoCEv2AxiStreamRdmaCore Entity Reference

Inheritance diagram for RoCEv2AxiStreamRdmaCore:

Collaboration diagram for RoCEv2AxiStreamRdmaCore:

Entities
RoCEv2AxiStreamRdmaCore.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
RoCEv2Pkg	Package <RoCEv2Pkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
RING_SLOTS_G	positive := 16
ROCE_CLK_FREQ_G	real := 156 . 25E + 6
DISPATCH_COUNTER_BITS_G	positive := 24

Ports
roceClk	in	sl
roceRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
workReqMaster	out	RoCEv2WorkReqMasterType
workReqSlave	in	RoCEv2WorkReqSlaveType
workCompMaster	in	RoCEv2WorkCompMasterType
workCompSlave	out	RoCEv2WorkCompSlaveType
dmaReadReqMaster	in	RoCEv2DmaReadReqMasterType
dmaReadReqSlave	out	RoCEv2DmaReadReqSlaveType
dmaReadRespMaster	out	RoCEv2DmaReadRespMasterType
dmaReadRespSlave	in	RoCEv2DmaReadRespSlaveType
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2AxiStreamRdmaCore.vhd