SURF
Loading...
Searching...
No Matches
Constants | Instantiations | Processes | Records | Signals | Types
RoCEv2AxiStreamRdmaCore.rtl Architecture Reference
Architecture >> RoCEv2AxiStreamRdmaCore::rtl

Processes

regComb  ( axilReadMaster , axilWriteMaster , fillR , monBandwidth , monBandwidthMax , monBandwidthMin , monFrameCnt , monFrameRate , monFrameRateMax , monFrameRateMin , monFrameSize , monFrameSizeMax , monFrameSizeMin , r , servR , workCompMaster )
seq  ( roceClk , roceRst )
fillComb  ( fifoMaster , fillR , r )
fillSeq  ( roceClk , roceRst )
serveComb  ( dmaReadReqMaster , dmaReadRespSlave , fillR , r , ramDoutb , servR )
serveSeq  ( roceClk , roceRst )
dispComb  ( dispR , fillR , r , workReqSlave )
dispSeq  ( roceClk , roceRst )

Constants

AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > TDATA_ROCE_NUM_BYTES_C , tKeepMode = > TKEEP_NORMAL_C , tDestBits = > 0 )
MAX_BEATS_C  positive := 128
MAX_FRAME_BYTES_C  positive := MAX_BEATS_C* 32
SLOT_BITS_C  positive := log2 ( RING_SLOTS_G )
BEAT_BITS_C  positive := log2 ( MAX_BEATS_C )
RAM_ADDR_W_C  positive := SLOT_BITS_C+ BEAT_BITS_C
RAM_DATA_W_C  positive := 256 + 32
PTR_W_C  positive := DISPATCH_COUNTER_BITS_G
REP_BYTE_CNT_W_C  positive := 14
REG_INIT_C  RegType := ( dispatchEnable = > ' 0 ' , rKey = > ( others = > ' 0 ' ) , lKey = > ( others = > ' 0 ' ) , sQpn = > ( others = > ' 0 ' ) , dQpn = > ( others = > ' 0 ' ) , rAddr = > ( others = > ' 0 ' ) , addrWrapCount = > ( others = > ' 0 ' ) , resetCounters = > ' 0 ' , successCounter = > ( others = > ' 0 ' ) , unsuccessCounter = > ( others = > ' 0 ' ) , compState = > ST0_IDLE , status = > ( others = > ' 0 ' ) , workCompSlave = > ROCE_WORK_COMP_SLAVE_INIT_C , freePtr = > ( others = > ' 0 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )
FILL_INIT_C  FillRegType := ( state = > F_IDLE , fillPtr = > ( others = > ' 0 ' ) , beatIdx = > ( others = > ' 0 ' ) , drainedBytes = > ( others = > ' 0 ' ) , slotErrAcc = > ' 0 ' , oversizeCount = > ( others = > ' 0 ' ) , wea = > ' 0 ' , addra = > ( others = > ' 0 ' ) , dina = > ( others = > ' 0 ' ) , lastIdx = > ( others = > ( others = > ' 0 ' ) ) , slotLen = > ( others = > ( others = > ' 0 ' ) ) , slotErr = > ( others = > ' 0 ' ) , fifoSlave = > AXI_STREAM_SLAVE_FORCE_C )
SERVE_INIT_C  ServeRegType := ( state = > S_IDLE , slot = > ( others = > ' 0 ' ) , idx = > ( others = > ' 0 ' ) , lastIdx = > ( others = > ' 0 ' ) , slotErrLatched = > ' 0 ' , reqInit = > ( others = > ' 0 ' ) , reqSqpn = > ( others = > ' 0 ' ) , reqWrId = > ( others = > ' 0 ' ) , dmaReadCnt = > ( others = > ' 0 ' ) , dmaReadReqSlave = > ROCE_DMA_READ_REQ_SLAVE_INIT_C , dmaReadRespMaster = > ROCE_DMA_READ_RESP_MASTER_INIT_C )
DISP_INIT_C  DispRegType := ( state = > ST0_IDLE , sendPtr = > ( others = > ' 0 ' ) , addrCount = > ( others = > ' 0 ' ) , txMaster = > ROCE_WORK_REQ_MASTER_INIT_C )

Types

SlotIdxArray  ( 0 to RING_SLOTS_G- 1 ) slv ( BEAT_BITS_C- 1 downto 0 )
SlotLenArray  ( 0 to RING_SLOTS_G- 1 ) slv ( REP_BYTE_CNT_W_C- 1 downto 0 )
CompStateType  ( ST0_IDLE , ST1_RECEIVED )
FillStateType  ( F_IDLE , F_DRAIN , F_DROP , F_DONE )
ServeStateType  ( S_IDLE , S_READ , S_PRES )
DispStateType  ( ST0_IDLE , ST1_SENDING )

Signals

r  RegType := REG_INIT_C
rin  RegType
fifoMaster  AxiStreamMasterType
fifoSlave  AxiStreamSlaveType
fifoRst  sl
fifoSAxisSlave  AxiStreamSlaveType
monFrameCnt  slv ( 63 downto 0 )
monFrameSize  slv ( 31 downto 0 )
monFrameSizeMax  slv ( 31 downto 0 )
monFrameSizeMin  slv ( 31 downto 0 )
monFrameRate  slv ( 31 downto 0 )
monFrameRateMax  slv ( 31 downto 0 )
monFrameRateMin  slv ( 31 downto 0 )
monBandwidth  slv ( 63 downto 0 )
monBandwidthMax  slv ( 63 downto 0 )
monBandwidthMin  slv ( 63 downto 0 )
monRst  sl
fillR  FillRegType := FILL_INIT_C
fillRin  FillRegType
servR  ServeRegType := SERVE_INIT_C
servRin  ServeRegType
ramAddrb  slv ( RAM_ADDR_W_C- 1 downto 0 ) := ( others = > ' 0 ' )
ramDoutb  slv ( RAM_DATA_W_C- 1 downto 0 )
dispR  DispRegType := DISP_INIT_C
dispRin  DispRegType

Records

RegType 
FillRegType 
ServeRegType 
DispRegType 

Instantiations

u_repackfifo  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_axistreammon  AxiStreamMon <Entity AxiStreamMon>
u_replayram  SimpleDualPortRam <Entity SimpleDualPortRam>
The documentation for this design unit was generated from the following file: