RoCEv2Engine Entity Reference

Inheritance diagram for RoCEv2Engine:

Collaboration diagram for RoCEv2Engine:

Entities
RoCEv2Engine.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
SsiPkg	Package <SsiPkg>
RoCEv2Pkg	Package <RoCEv2Pkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '

Ports
clk	in	sl
rst	in	sl
workReqMaster	in	RoCEv2WorkReqMasterType
workReqSlave	out	RoCEv2WorkReqSlaveType
workCompMaster	out	RoCEv2WorkCompMasterType
workCompSlave	in	RoCEv2WorkCompSlaveType
obUdpMaster	in	AxiStreamMasterType
obUdpSlave	out	AxiStreamSlaveType
ibUdpMaster	out	AxiStreamMasterType
ibUdpSlave	in	AxiStreamSlaveType
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
dmaReadRespMaster	in	RoCEv2DmaReadRespMasterType
dmaReadRespSlave	out	RoCEv2DmaReadRespSlaveType
dmaReadReqMaster	out	RoCEv2DmaReadReqMasterType
dmaReadReqSlave	in	RoCEv2DmaReadReqSlaveType
cnp_received	out	sl

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2Engine.vhd