RoCEv2Engine.mapping Architecture Reference

Architecture >> RoCEv2Engine::mapping

Components
mkAxiSTransportLayer

Signals
roceRstN	sl
obUdpRoceMaster_tValid	sl
obUdpRoceMaster_tData	slv ( 255 downto 0 )
obUdpRoceMaster_tKeep	slv ( 31 downto 0 )
obUdpRoceMaster_tFirst	sl
obUdpRoceMaster_tLast	sl
obUdpRoceMaster_tUser	slv ( 1 downto 0 )
obUdpRoceSlave_tReady	sl
ibUdpRoceMaster_tValid	sl
ibUdpRoceMaster_tData	slv ( 255 downto 0 )
ibUdpRoceMaster_tKeep	slv ( 31 downto 0 )
ibUdpRoceMaster_tFirst	sl
ibUdpRoceMaster_tLast	sl
ibUdpRoceMaster_tUser	slv ( 1 downto 0 )
ibUdpRoceSlave_tReady	sl
obUdpRoceMaster	AxiStreamMasterType
obUdpRoceSlave	AxiStreamSlaveType
ibUdpRoceMaster	AxiStreamMasterType
ibUdpRoceSlave	AxiStreamSlaveType
s_axisMetaDataReqMaster	AxiStreamMasterType
s_axisMetaDataReqSlave	AxiStreamSlaveType
s_axisMetaDataRespMaster	AxiStreamMasterType
s_axisMetaDataRespSlave	AxiStreamSlaveType
s_cnp_received	sl
s_softRst	sl

Instantiations
axistreamresize_inst	RoceResizeAndSwap <Entity RoceResizeAndSwap>
axistreamresize_1	RoceResizeAndSwap <Entity RoceResizeAndSwap>
masteraxistreamipintegrator_inst	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
slaveaxistreamipintegrator_inst	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
mkaxistransportlayer_1	mkaxistransportlayer
roceconfigurator_1	RoceConfigurator <Entity RoceConfigurator>

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2Engine.vhd