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Pgp2fcLane_tb.Pgp2fcLane_tb Architecture Reference
Architecture >> Pgp2fcLane_tb::Pgp2fcLane_tb

Processes

PROCESS_344 
PROCESS_345 
PROCESS_346 
PROCESS_347 
PROCESS_348 
PROCESS_349  ( locClk )
PROCESS_350  ( locClk )

Constants

RCEG3_AXIS_DMA_CONFIG_G  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 4 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )

Signals

locClk  sl
locClkRst  sl
slowClk  sl
slowClkRst  sl
enable  sl
txEnable  slv ( VC_CHANNELS- 1 downto 0 )
txBusy  slv ( VC_CHANNELS- 1 downto 0 )
txLength  Slv32Array ( VC_CHANNELS- 1 downto 0 )
prbsTxMasters  AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
prbsTxSlaves  AxiStreamSlaveArray ( 3 downto 0 )
iprbsTxMasters  AxiStreamMasterArray ( VC_CHANNELS- 1 downto 0 )
iprbsTxSlaves  AxiStreamSlaveArray ( VC_CHANNELS- 1 downto 0 )
lprbsTxMasters  AxiStreamMasterArray ( VC_CHANNELS- 1 downto 0 )
lprbsTxSlaves  AxiStreamSlaveArray ( VC_CHANNELS- 1 downto 0 )
prbsRxMasters  AxiStreamMasterArray ( 3 downto 0 )
prbsRxSlaves  AxiStreamSlaveArray ( VC_CHANNELS- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
prbsRxCtrl  AxiStreamCtrlArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CTRL_INIT_C )
iprbsRxMasters  AxiStreamMasterArray ( VC_CHANNELS- 1 downto 0 )
iprbsRxSlaves  AxiStreamSlaveArray ( VC_CHANNELS- 1 downto 0 )
iprbsRxCtrl  AxiStreamCtrlArray ( VC_CHANNELS- 1 downto 0 )
updatedResults  slv ( VC_CHANNELS- 1 downto 0 )
errMissedPacket  slv ( VC_CHANNELS- 1 downto 0 )
errLength  slv ( VC_CHANNELS- 1 downto 0 )
errEofe  slv ( VC_CHANNELS- 1 downto 0 )
errDataBus  slv ( VC_CHANNELS- 1 downto 0 )
errWordCnt  Slv32Array ( VC_CHANNELS- 1 downto 0 )
packetRate  Slv32Array ( VC_CHANNELS- 1 downto 0 )
packetLength  Slv32Array ( VC_CHANNELS- 1 downto 0 )
phyTxLaneOut  Pgp2fcTxPhyLaneOutType
phyRxLaneIn  Pgp2fcRxPhyLaneInType
pgpTxIn  Pgp2fcTxInType
pgpTxOut  Pgp2fcTxOutType
pgpRxIn  Pgp2fcRxInType
pgpRxOut  Pgp2fcRxOutType
fcTxSend  sl := ' 0 '
fcTxWord  slv ( FC_WORDS* 16 - 1 downto 0 ) := ( others = > ' 0 ' )
fcRxRecv  sl
fcRxWord  slv ( FC_WORDS* 16 - 1 downto 0 )
fcInterval  integer range 0 to FC_INTERVAL- 1 := FC_START_VAL
fcCounter  unsigned ( FC_WORDS* 16 - 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations

u_ssiprbstx  SsiPrbsTx <Entity SsiPrbsTx>
u_txfifo  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_pgptxmux  AxiStreamDeMux <Entity AxiStreamDeMux>
u_pgp  Pgp2fcLane <Entity Pgp2fcLane>
axistreamfifo_rx  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_ssiprbsrx  SsiPrbsRx <Entity SsiPrbsRx>

The documentation for this design unit was generated from the following file: