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Pgp2bGth7Fixedlat.rtl Architecture Reference
Architecture >> Pgp2bGth7Fixedlat::rtl

Signals

gtRxResetDone  sl
gtRxResetDoneL  sl
gtRxUserReset  sl
gtRxData  slv ( 19 downto 0 )
dataValid  sl
phyRxLanesIn  Pgp2bRxPhyLaneInArray ( 0 to 0 )
phyRxLanesOut  Pgp2bRxPhyLaneOutArray ( 0 to 0 )
phyRxReady  sl
phyRxInit  sl
gtTxOutClk  sl
gtTxUsrClk  sl
gtTxResetDone  sl
phyTxLanesOut  Pgp2bTxPhyLaneOutArray ( 0 to 0 )
phyTxReady  sl
stableRst  sl
drpGnt  sl
drpRdy  sl
drpEn  sl
drpWe  sl
drpAddr  slv ( 8 downto 0 )
drpDi  slv ( 15 downto 0 )
drpDo  slv ( 15 downto 0 )

Instantiations

u_pgp2blane  Pgp2bLane <Entity Pgp2bLane>
decoder8b10b_1  Decoder8b10b <Entity Decoder8b10b>
gth7core_1  Gth7Core <Entity Gth7Core>
u_axilitetodrp  AxiLiteToDrp <Entity AxiLiteToDrp>
u_rstsync  RstSync <Entity RstSync>

The documentation for this design unit was generated from the following file: