Pgp2bLane Entity Reference

Inheritance diagram for Pgp2bLane:

Collaboration diagram for Pgp2bLane:

Entities
Pgp2bLane.Pgp2bLane	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
LANE_CNT_G	integer range 1 to 2 := 1
VC_INTERLEAVE_G	integer := 1
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true

Ports
pgpTxClkEn	in	sl := ' 1 '
pgpTxClk	in	sl := ' 0 '
pgpTxClkRst	in	sl := ' 0 '
pgpTxIn	in	Pgp2bTxInType := PGP2B_TX_IN_INIT_C
pgpTxOut	out	Pgp2bTxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
phyTxLanesOut	out	Pgp2bTxPhyLaneOutArray ( 0 to LANE_CNT_G- 1 )
phyTxReady	in	sl := ' 0 '
pgpRxClkEn	in	sl := ' 1 '
pgpRxClk	in	sl := ' 0 '
pgpRxClkRst	in	sl := ' 0 '
pgpRxIn	in	Pgp2bRxInType := PGP2B_RX_IN_INIT_C
pgpRxOut	out	Pgp2bRxOutType
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed	out	AxiStreamMasterType
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
phyRxLanesOut	out	Pgp2bRxPhyLaneOutArray ( 0 to LANE_CNT_G- 1 )
phyRxLanesIn	in	Pgp2bRxPhyLaneInArray ( 0 to LANE_CNT_G- 1 ) := ( others = > PGP2B_RX_PHY_LANE_IN_INIT_C )
phyRxReady	in	sl := ' 0 '
phyRxInit	out	sl

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd