Gth7Core Entity Reference

Inheritance diagram for Gth7Core:

Collaboration diagram for Gth7Core:

Entities
Gth7Core.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_GTRESET_SPEEDUP_G	string := " FALSE "
SIM_VERSION_G	string := " 2.0 "
SIMULATION_G	boolean := false
STABLE_CLOCK_PERIOD_G	real := 4 . 0E - 9
CPLL_REFCLK_SEL_G	bit_vector := " 001 "
CPLL_FBDIV_G	integer := 4
CPLL_FBDIV_45_G	integer := 5
CPLL_REFCLK_DIV_G	integer := 1
RXOUT_DIV_G	integer := 2
TXOUT_DIV_G	integer := 2
RX_CLK25_DIV_G	integer := 5
TX_CLK25_DIV_G	integer := 5
PMA_RSV_G	bit_vector := X " 00000080 "
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 0002007FE1000C2200018 "
TX_PLL_G	string := " CPLL "
RX_PLL_G	string := " CPLL "
TX_EXT_DATA_WIDTH_G	integer := 16
TX_INT_DATA_WIDTH_G	integer := 20
TX_8B10B_EN_G	boolean := true
RX_EXT_DATA_WIDTH_G	integer := 16
RX_INT_DATA_WIDTH_G	integer := 20
RX_8B10B_EN_G	boolean := true
TX_BUF_EN_G	boolean := true
TX_OUTCLK_SRC_G	string := " PLLREFCLK "
TX_DLY_BYPASS_G	sl := ' 1 '
TX_PHASE_ALIGN_G	string := " AUTO "
TX_BUF_ADDR_MODE_G	string := " FAST "
RX_BUF_EN_G	boolean := true
RX_OUTCLK_SRC_G	string := " PLLREFCLK "
RX_USRCLK_SRC_G	string := " RXOUTCLK "
RX_DLY_BYPASS_G	sl := ' 1 '
RX_DDIEN_G	sl := ' 0 '
RX_BUF_ADDR_MODE_G	string := " FAST "
RX_ALIGN_MODE_G	string := " GT "
ALIGN_COMMA_DOUBLE_G	string := " FALSE "
ALIGN_COMMA_ENABLE_G	bit_vector := " 1111111111 "
ALIGN_COMMA_WORD_G	integer := 2
ALIGN_MCOMMA_DET_G	string := " FALSE "
ALIGN_MCOMMA_VALUE_G	bit_vector := " 1010000011 "
ALIGN_MCOMMA_EN_G	sl := ' 0 '
ALIGN_PCOMMA_DET_G	string := " FALSE "
ALIGN_PCOMMA_VALUE_G	bit_vector := " 0101111100 "
ALIGN_PCOMMA_EN_G	sl := ' 0 '
SHOW_REALIGN_COMMA_G	string := " FALSE "
RXSLIDE_MODE_G	string := " PCS "
FIXED_COMMA_EN_G	slv ( 3 downto 0 ) := " 0011 "
FIXED_ALIGN_COMMA_0_G	slv := " ----------0101111100 "
FIXED_ALIGN_COMMA_1_G	slv := " ----------1010000011 "
FIXED_ALIGN_COMMA_2_G	slv := " XXXXXXXXXXXXXXXXXXXX "
FIXED_ALIGN_COMMA_3_G	slv := " XXXXXXXXXXXXXXXXXXXX "
RX_DISPERR_SEQ_MATCH_G	string := " TRUE "
DEC_MCOMMA_DETECT_G	string := " TRUE "
DEC_PCOMMA_DETECT_G	string := " TRUE "
DEC_VALID_COMMA_ONLY_G	string := " FALSE "
CBCC_DATA_SOURCE_SEL_G	string := " DECODED "
CLK_COR_SEQ_2_USE_G	string := " FALSE "
CLK_COR_KEEP_IDLE_G	string := " FALSE "
CLK_COR_MAX_LAT_G	integer := 9
CLK_COR_MIN_LAT_G	integer := 7
CLK_COR_PRECEDENCE_G	string := " TRUE "
CLK_COR_REPEAT_WAIT_G	integer := 0
CLK_COR_SEQ_LEN_G	integer := 1
CLK_COR_SEQ_1_ENABLE_G	bit_vector := " 1111 "
CLK_COR_SEQ_1_1_G	bit_vector := " 0100000000 "
CLK_COR_SEQ_1_2_G	bit_vector := " 0000000000 "
CLK_COR_SEQ_1_3_G	bit_vector := " 0000000000 "
CLK_COR_SEQ_1_4_G	bit_vector := " 0000000000 "
CLK_CORRECT_USE_G	string := " FALSE "
CLK_COR_SEQ_2_ENABLE_G	bit_vector := " 0000 "
CLK_COR_SEQ_2_1_G	bit_vector := " 0100000000 "
CLK_COR_SEQ_2_2_G	bit_vector := " 0000000000 "
CLK_COR_SEQ_2_3_G	bit_vector := " 0000000000 "
CLK_COR_SEQ_2_4_G	bit_vector := " 0000000000 "
RX_CHAN_BOND_EN_G	boolean := false
RX_CHAN_BOND_MASTER_G	boolean := false
CHAN_BOND_KEEP_ALIGN_G	string := " FALSE "
CHAN_BOND_MAX_SKEW_G	integer := 1
CHAN_BOND_SEQ_LEN_G	integer := 1
CHAN_BOND_SEQ_1_1_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_2_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_3_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_4_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_ENABLE_G	bit_vector := " 1111 "
CHAN_BOND_SEQ_2_1_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_2_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_3_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_4_G	bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_ENABLE_G	bit_vector := " 0000 "
CHAN_BOND_SEQ_2_USE_G	string := " FALSE "
FTS_DESKEW_SEQ_ENABLE_G	bit_vector := " 1111 "
FTS_LANE_DESKEW_CFG_G	bit_vector := " 1111 "
FTS_LANE_DESKEW_EN_G	string := " FALSE "
RX_EQUALIZER_G	string := " LPM "
RX_CM_TRIM_G	bit_vector := " 1000 "
RX_DFE_LPM_CFG_G	bit_vector := x " 0080 "
RXDFELFOVRDEN_G	sl := ' 0 '
RXDFEXYDEN_G	sl := ' 1 '

Ports
stableClkIn	in	sl
cPllRefClkIn	in	sl := ' 0 '
cPllLockOut	out	sl
qPllRefClkIn	in	sl := ' 0 '
qPllClkIn	in	sl := ' 0 '
qPllLockIn	in	sl := ' 0 '
qPllRefClkLostIn	in	sl := ' 0 '
qPllResetOut	out	sl
gtRxRefClkBufg	in	sl := ' 0 '
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl
rxOutClkOut	out	sl
rxUsrClkIn	in	sl
rxUsrClk2In	in	sl
rxUserRdyOut	out	sl
rxMmcmResetOut	out	sl
rxMmcmLockedIn	in	sl := ' 1 '
rxUserResetIn	in	sl
rxResetDoneOut	out	sl
rxDataValidIn	in	sl := ' 1 '
rxSlideIn	in	sl := ' 0 '
rxDataOut	out	slv ( RX_EXT_DATA_WIDTH_G- 1 downto 0 )
rxCharIsKOut	out	slv ( ( RX_EXT_DATA_WIDTH_G/ 8 ) - 1 downto 0 )
rxDecErrOut	out	slv ( ( RX_EXT_DATA_WIDTH_G/ 8 ) - 1 downto 0 )
rxDispErrOut	out	slv ( ( RX_EXT_DATA_WIDTH_G/ 8 ) - 1 downto 0 )
rxPolarityIn	in	sl := ' 0 '
rxBufStatusOut	out	slv ( 2 downto 0 )
rxChBondLevelIn	in	slv ( 2 downto 0 ) := " 000 "
rxChBondIn	in	slv ( 4 downto 0 ) := " 00000 "
rxChBondOut	out	slv ( 4 downto 0 )
txOutClkOut	out	sl
txUsrClkIn	in	sl
txUsrClk2In	in	sl
txUserRdyOut	out	sl
txMmcmResetOut	out	sl
txMmcmLockedIn	in	sl := ' 1 '
txUserResetIn	in	sl
txResetDoneOut	out	sl
txDataIn	in	slv ( TX_EXT_DATA_WIDTH_G- 1 downto 0 )
txCharIsKIn	in	slv ( ( TX_EXT_DATA_WIDTH_G/ 8 ) - 1 downto 0 )
txBufStatusOut	out	slv ( 1 downto 0 )
txPolarityIn	in	sl := ' 0 '
txPowerDown	in	slv ( 1 downto 0 ) := " 00 "
rxPowerDown	in	slv ( 1 downto 0 ) := " 00 "
loopbackIn	in	slv ( 2 downto 0 ) := " 000 "
txPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
drpGnt	out	sl
drpRdy	out	sl
drpEn	in	sl := ' 0 '
drpWe	in	sl := ' 0 '
drpAddr	in	slv ( 8 downto 0 ) := " 000000000 "
drpDi	in	slv ( 15 downto 0 ) := X " 0000 "
drpDo	out	slv ( 15 downto 0 )

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gth7/rtl/Gth7Core.vhd