Architecture >> Gth7Core::rtl
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RX_SYSCLK_SEL_C | slv := ite ( RX_PLL_G = " CPLL " , " 00 " , " 11 " ) |
TX_SYSCLK_SEL_C | slv := ite ( TX_PLL_G = " CPLL " , " 00 " , " 11 " ) |
RX_XCLK_SEL_C | string := ite ( RX_BUF_EN_G , " RXREC " , " RXUSR " ) |
TX_XCLK_SEL_C | string := ite ( TX_BUF_EN_G , " TXOUT " , " TXUSR " ) |
RX_OUTCLK_SEL_C | bit_vector := getOutClkSelVal ( RX_OUTCLK_SRC_G ) |
TX_OUTCLK_SEL_C | bit_vector := getOutClkSelVal ( TX_OUTCLK_SRC_G ) |
RX_DATA_WIDTH_C | integer := getDataWidth ( RX_8B10B_EN_G , RX_EXT_DATA_WIDTH_G ) |
TX_DATA_WIDTH_C | integer := getDataWidth ( TX_8B10B_EN_G , TX_EXT_DATA_WIDTH_G ) |
WAIT_TIME_CDRLOCK_C | integer := ite ( SIM_GTRESET_SPEEDUP_G = " TRUE " , 16 , 65520 ) |
RX_INT_DATAWIDTH_C | integer := ( RX_INT_DATA_WIDTH_G/ 32 ) |
TX_INT_DATAWIDTH_C | integer := ( TX_INT_DATA_WIDTH_G/ 32 ) |
The documentation for this design unit was generated from the following file:
- xilinx/7Series/gth7/rtl/Gth7Core.vhd