Gth7RecClkMonitor Entity Reference

Inheritance diagram for Gth7RecClkMonitor:

Entities
Gth7RecClkMonitor.RTL	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
COUNTER_UPPER_VALUE	integer := 20
GCLK_COUNTER_UPPER_VALUE	integer := 20
CLOCK_PULSES	integer := 5000
EXAMPLE_SIMULATION	integer := 0

Ports
GT_RST	in	std_logic
REF_CLK	in	std_logic
RX_REC_CLK0	in	std_logic
SYSTEM_CLK	in	std_logic
PLL_LK_DET	in	std_logic
RECCLK_STABLE	out	std_logic
EXEC_RESTART	out	std_logic

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd