HtspCoreTb.testbed Architecture Reference

Architecture >> HtspCoreTb::testbed

Processes
PHY_AXIS	( rxMaster )
PROCESS_247	( clk )
PROCESS_248	( failed , passed )
test

Constants
TPD_G	time := 1 ns
PRBS_SEED_SIZE_C	positive := 512
NUM_VC_C	positive := 4
TX_MAX_PAYLOAD_SIZE_C	positive := 2048
CHOKE_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
PKT_LEN_C	slv ( 31 downto 0 ) := x " 000000FF "

Signals
txusrclk2	sl := ' 0 '
clk	sl := ' 0 '
rst	sl := ' 1 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C
phyTxMaster	AxiStreamMasterType
phyTxSlave	AxiStreamSlaveType
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType
phyMaster	AxiStreamMasterType
rxMaster	AxiStreamMasterType
phyRxMaster	AxiStreamMasterType
htspTxMasters	AxiStreamMasterArray ( NUM_VC_C- 1 downto 0 )
htspTxSlaves	AxiStreamSlaveArray ( NUM_VC_C- 1 downto 0 )
htspRxMasters	AxiStreamMasterArray ( NUM_VC_C- 1 downto 0 )
htspRxCtrl	AxiStreamCtrlArray ( NUM_VC_C- 1 downto 0 )
rxMasters	AxiStreamMasterArray ( NUM_VC_C- 1 downto 0 )
rxSlaves	AxiStreamSlaveArray ( NUM_VC_C- 1 downto 0 )
updateDet	slv ( NUM_VC_C- 1 downto 0 )
errorDet	slv ( NUM_VC_C- 1 downto 0 )
passed	sl := ' 0 '
failed	sl := ' 0 '

Instantiations
u_clk_0	ClkRst <Entity ClkRst>
u_clk_1	ClkRst <Entity ClkRst>
u_core	HtspCore <Entity HtspCore>
u_tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_rx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_bottleneck	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>

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The documentation for this design unit was generated from the following file:

• protocols/htsp/core/tb/HtspCoreTb.vhd