SURF
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HtspCore Entity Reference
+ Inheritance diagram for HtspCore:
+ Collaboration diagram for HtspCore:

Entities

HtspCore.mapping  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
HtspPkg  Package <HtspPkg>

Generics

TPD_G  time := 1 ns
NUM_VC_G  positive range 1 to 16 := 4
TX_MAX_PAYLOAD_SIZE_G  positive := 8192
LOOPBACK_G  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
RX_POLARITY_G  slv ( 9 downto 0 ) := ( others = > ' 0 ' )
TX_POLARITY_G  slv ( 9 downto 0 ) := ( others = > ' 0 ' )
TX_DIFF_CTRL_G  Slv5Array ( 9 downto 0 ) := ( others = > " 11000 " )
TX_PRE_CURSOR_G  Slv5Array ( 9 downto 0 ) := ( others = > " 00000 " )
TX_POST_CURSOR_G  Slv5Array ( 9 downto 0 ) := ( others = > " 00000 " )
AXIL_WRITE_EN_G  boolean := false
AXIL_BASE_ADDR_G  slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXIL_CLK_FREQ_G  real := 156 . 25E + 6

Ports

htspClk   in   sl
htspRst   in   sl
htspTxIn   in   HtspTxInType := HTSP_TX_IN_INIT_C
htspTxOut   out   HtspTxOutType
htspTxMasters   in   AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
htspTxSlaves   out   AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
htspRxIn   in   HtspRxInType := HTSP_RX_IN_INIT_C
htspRxOut   out   HtspRxOutType
htspRxMasters   out   AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
htspRxCtrl   in   AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
phyTxRdy   in   sl
phyTxMaster   out   AxiStreamMasterType
phyTxSlave   in   AxiStreamSlaveType
phyRxRdy   in   sl
phyRxMaster   in   AxiStreamMasterType
localMac   in   slv ( 47 downto 0 ) := x " 01_02_03_56_44_00 "
loopback   out   slv ( 2 downto 0 )
rxPolarity   out   slv ( 9 downto 0 )
txPolarity   out   slv ( 9 downto 0 )
txDiffCtrl   out   Slv5Array ( 9 downto 0 )
txPreCursor   out   Slv5Array ( 9 downto 0 )
txPostCursor   out   Slv5Array ( 9 downto 0 )
phyUsrRst   out   sl
axilClk   in   sl := ' 0 '
axilRst   in   sl := ' 0 '
axilReadMaster   in   AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out   AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster   in   AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out   AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

The documentation for this design unit was generated from the following file: