HtspCore.mapping Architecture Reference

Architecture >> HtspCore::mapping

Processes
PROCESS_117	( htspClk )
PROCESS_254	( htspClk )

Signals
locRxLinkReady	sl
remRxFifoCtrl	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
remRxLinkReady	sl
htspTxInInt	HtspTxInType
htspTxOutInt	HtspTxOutType
htspRxInInt	HtspRxInType
htspRxOutInt	HtspRxOutType
broadcastMac	slv ( 47 downto 0 )
remoteMac	slv ( 47 downto 0 )
localMac	slv ( 47 downto 0 )
etherType	slv ( 15 downto 0 )
remRxFifoCtrlReg	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_INIT_C )
remRxLinkReadyReg	sl := ' 0 '
locRxLinkReadyReg	sl := ' 0 '

Attributes
dont_touch	string
dont_touch	signal is " TRUE "

Instantiations
u_tx	HtspTx <Entity HtspTx>
u_rx	HtspRx <Entity HtspRx>
u_axilite	HtspAxiL <Entity HtspAxiL>
u_tx	HtspTx <Entity HtspTx>
u_rx	HtspRx <Entity HtspRx>
u_axilite	HtspAxiL <Entity HtspAxiL>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/HtspCore.vhd
• protocols/htsp/core/rtl/HtspCore.vhd