HtspAxiL Entity Reference

Inheritance diagram for HtspAxiL:

Collaboration diagram for HtspAxiL:

Entities
HtspAxiL.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
HtspPkg	Package <HtspPkg>

Generics
TPD_G	time := 1 ns
WRITE_EN_G	boolean := false
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXIL_CLK_FREQ_G	real := 156 . 25E + 6
LOOPBACK_G	slv ( 2 downto 0 ) := ( others = > ' 0 ' )
RX_POLARITY_G	slv ( 9 downto 0 ) := ( others = > ' 0 ' )
TX_POLARITY_G	slv ( 9 downto 0 ) := ( others = > ' 0 ' )
TX_DIFF_CTRL_G	Slv5Array ( 9 downto 0 ) := ( others = > " 11000 " )
TX_PRE_CURSOR_G	Slv5Array ( 9 downto 0 ) := ( others = > " 00000 " )
TX_POST_CURSOR_G	Slv5Array ( 9 downto 0 ) := ( others = > " 00000 " )

Ports
htspClk	in	sl
htspRst	in	sl
htspTxIn	out	HtspTxInType
htspTxOut	in	HtspTxOutType
locTxIn	in	HtspTxInType := HTSP_TX_IN_INIT_C
htspRxIn	out	HtspRxInType
htspRxOut	in	HtspRxOutType
locRxIn	in	HtspRxInType := HTSP_RX_IN_INIT_C
remoteMac	in	slv ( 47 downto 0 )
localMac	in	slv ( 47 downto 0 )
broadcastMac	out	slv ( 47 downto 0 )
etherType	out	slv ( 15 downto 0 )
loopback	out	slv ( 2 downto 0 )
rxPolarity	out	slv ( 9 downto 0 )
txPolarity	out	slv ( 9 downto 0 )
txDiffCtrl	out	Slv5Array ( 9 downto 0 )
txPreCursor	out	Slv5Array ( 9 downto 0 )
txPostCursor	out	Slv5Array ( 9 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/htsp/core/rtl/HtspAxiL.vhd