Architecture >> HtspCaui4GtyTb::testbed

Constants
TPD_G	time := 1 ns
PRBS_SEED_SIZE_C	positive := 512
NUM_VC_C	positive := 4
TX_MAX_PAYLOAD_SIZE_C	positive := 1024
CHOKE_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
PKT_LEN_C	slv ( 31 downto 0 ) := x " 000000FF "

Signals
htspTxIn	HtspTxInType := HTSP_TX_IN_INIT_C
htspTxOut	HtspTxOutType
htspRxIn	HtspRxInType := HTSP_RX_IN_INIT_C
htspRxOut	HtspRxOutType
htspTxMasters	AxiStreamMasterArray ( NUM_VC_C- 1 downto 0 )
htspTxSlaves	AxiStreamSlaveArray ( NUM_VC_C- 1 downto 0 )
htspRxMasters	AxiStreamMasterArray ( NUM_VC_C- 1 downto 0 )
htspRxCtrl	AxiStreamCtrlArray ( NUM_VC_C- 1 downto 0 )
rxMasters	AxiStreamMasterArray ( NUM_VC_C- 1 downto 0 )
rxSlaves	AxiStreamSlaveArray ( NUM_VC_C- 1 downto 0 )
updateDet	slv ( NUM_VC_C- 1 downto 0 )
errorDet	slv ( NUM_VC_C- 1 downto 0 )
loopbackP	slv ( 3 downto 0 )
loopbackN	slv ( 3 downto 0 )
stableClk	sl := ' 0 '
stableRst	sl := ' 1 '
gtRefClkP	sl := ' 0 '
gtRefClkN	sl := ' 1 '
htspClk	sl := ' 0 '
htspRst	sl := ' 1 '
passed	sl := ' 0 '
failed	sl := ' 0 '

Instantiations
u_stableclk	ClkRst <Entity ClkRst>
u_gtrefclk	ClkRst <Entity ClkRst>
u_core	HtspCaui4Gty <Entity HtspCaui4Gty>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_bottleneck	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>

The documentation for this design unit was generated from the following file:

Processes

Constants