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SURF
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Inheritance diagram for HtspCaui4Gty:
Collaboration diagram for HtspCaui4Gty:Entities | |
| HtspCaui4Gty.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| HtspPkg | Package <HtspPkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| SIM_SPEEDUP_G | boolean := false |
| ROGUE_SIM_EN_G | boolean := false |
| ROGUE_SIM_SIDEBAND_G | boolean := false |
| ROGUE_SIM_PORT_NUM_G | natural range 1024 to 49151 := 9000 |
| REFCLK_TYPE_G | string := " 161MHz " |
| NUM_VC_G | integer range 1 to 16 := 4 |
| TX_MAX_PAYLOAD_SIZE_G | positive := 8192 |
| LOOPBACK_G | slv ( 2 downto 0 ) := ( others = > ' 0 ' ) |
| RX_POLARITY_G | slv ( 3 downto 0 ) := ( others = > ' 0 ' ) |
| TX_POLARITY_G | slv ( 3 downto 0 ) := ( others = > ' 0 ' ) |
| TX_DIFF_CTRL_G | Slv5Array ( 3 downto 0 ) := ( others = > " 11000 " ) |
| TX_PRE_CURSOR_G | Slv5Array ( 3 downto 0 ) := ( others = > " 00011 " ) |
| TX_POST_CURSOR_G | Slv5Array ( 3 downto 0 ) := ( others = > " 00011 " ) |
| AXIL_WRITE_EN_G | boolean := false |
| AXIL_CLK_FREQ_G | real := 156 . 25E + 6 |
Ports | ||
| stableClk | in | sl |
| stableRst | in | sl |
| htspClk | out | sl |
| htspRst | out | sl |
| htspRxIn | in | HtspRxInType := HTSP_RX_IN_INIT_C |
| htspRxOut | out | HtspRxOutType |
| htspTxIn | in | HtspTxInType := HTSP_TX_IN_INIT_C |
| htspTxOut | out | HtspTxOutType |
| htspTxMasters | in | AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 ) |
| htspTxSlaves | out | AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 ) |
| htspRxMasters | out | AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 ) |
| htspRxCtrl | in | AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) |
| htspRxSlaves | in | AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C ) |
| axilClk | in | sl := ' 0 ' |
| axilRst | in | sl := ' 0 ' |
| axilReadMaster | in | AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C |
| axilReadSlave | out | AxiLiteReadSlaveType |
| axilWriteMaster | in | AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C |
| axilWriteSlave | out | AxiLiteWriteSlaveType |
| localMac | in | slv ( 47 downto 0 ) := x " 01_02_03_56_44_00 " |
| gtRefClkP | in | sl |
| gtRefClkN | in | sl |
| gtRefClkOut | out | sl |
| gtRxP | in | slv ( 3 downto 0 ) |
| gtRxN | in | slv ( 3 downto 0 ) |
| gtTxP | out | slv ( 3 downto 0 ) |
| gtTxN | out | slv ( 3 downto 0 ) |