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HtspCaui4Gty.mapping Architecture Reference
Architecture >> HtspCaui4Gty::mapping

Processes

PROCESS_257  ( phyClk )

Signals

phyClk  sl
phyRst  sl
phyUsrRst  sl
htspRefClk  sl
phyRxMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
phyRxMasterReg0  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
phyRxMasterReg1  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
phyTxMaster  AxiStreamMasterType
phyTxSlave  AxiStreamSlaveType
loopback  slv ( 2 downto 0 )
rxPolarity  slv ( 3 downto 0 )
txPolarity  slv ( 3 downto 0 )
txDiffCtrl  Slv5Array ( 3 downto 0 )
txPreCursor  Slv5Array ( 3 downto 0 )
txPostCursor  Slv5Array ( 3 downto 0 )
stableReset  sl
phyReady  sl
rxFecCorInc  sl
rxFecUnCorInc  sl

Instantiations

u_htsprst  RstPipeline <Entity RstPipeline>
u_core  HtspCore <Entity HtspCore>
u_ip  Caui4GtyIpWrapper <Entity Caui4GtyIpWrapper>
u_rogue  RogueHtspSim <Entity RogueHtspSim>
u_htsprefclk  ibufds_gte4

The documentation for this design unit was generated from the following file: