GigEthGtx7.mapping Architecture Reference

Architecture >> GigEthGtx7::mapping

Components
GigEthGtx7Core

Constants
AXIL_NUM_C	integer := 2
ETH_AXIL_C	integer := 0
DRP_AXIL_C	integer := 1
AXIL_XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( AXIL_NUM_C- 1 downto 0 ) := ( ETH_AXIL_C = > ( baseAddr = > AXIL_BASE_ADDR_G+ X " 0000 " , addrBits = > 12 , connectivity = > X " FFFF " ) , DRP_AXIL_C = > ( baseAddr = > AXIL_BASE_ADDR_G+ X " 1000 " , addrBits = > 12 , connectivity = > X " FFFF " ) )

Signals
config	GigEthConfigType
status	GigEthStatusType
syncAxilReadMaster	AxiLiteReadMasterType
syncAxilReadSlave	AxiLiteReadSlaveType
syncAxilWriteMaster	AxiLiteWriteMasterType
syncAxilWriteSlave	AxiLiteWriteSlaveType
locAxilReadMasters	AxiLiteReadMasterArray ( AXIL_NUM_C- 1 downto 0 )
locAxilReadSlaves	AxiLiteReadSlaveArray ( AXIL_NUM_C- 1 downto 0 )
locAxilWriteMasters	AxiLiteWriteMasterArray ( AXIL_NUM_C- 1 downto 0 )
locAxilWriteSlaves	AxiLiteWriteSlaveArray ( AXIL_NUM_C- 1 downto 0 )
gmiiTxClk	sl
gmiiTxd	slv ( 7 downto 0 )
gmiiTxEn	sl
gmiiTxEr	sl
gmiiRxClk	sl
gmiiRxd	slv ( 7 downto 0 )
gmiiRxDv	sl
gmiiRxEr	sl
areset	sl
coreRst	sl
drpaddr	slv ( 8 downto 0 )
drpclk	sl
drpdi	slv ( 15 downto 0 )
drpdo	slv ( 15 downto 0 )
drpen	sl
drprdy	sl
drpwe	sl

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_pwruprst	PwrUpRst <Entity PwrUpRst>
u_mac	EthMacTop <Entity EthMacTop>
u_gigethgtx7core	gigethgtx7core
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>
u_gigethreg	GigEthReg <Entity GigEthReg>

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The documentation for this design unit was generated from the following file:

• ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd