GigEthGtx7 Entity Reference

Inheritance diagram for GigEthGtx7:

Collaboration diagram for GigEthGtx7:

Entities
GigEthGtx7.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
GigEthPkg	Package <GigEthPkg>

Generics
TPD_G	time := 1 ns
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
SYNTH_MODE_G	string := " inferred "
EN_AXI_REG_G	boolean := false
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := X " 00000000 "
AXIL_CLK_IS_SYSCLK125_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk	in	sl
dmaRst	in	sl
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
axiLiteClk	in	sl := ' 0 '
axiLiteRst	in	sl := ' 0 '
axiLiteReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave	out	AxiLiteReadSlaveType
axiLiteWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave	out	AxiLiteWriteSlaveType
sysClk62	in	sl
sysClk125	in	sl
sysRst125	in	sl
extRst	in	sl
phyReady	out	sl
sigDet	in	sl := ' 1 '
gtTxPolarity	in	sl := ' 0 '
gtRxPolarity	in	sl := ' 0 '
gtTxDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
gtTxPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
gtTxPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd