Architecture >> FirFilterMultiChannelTestWrapper::rtl

Signals
axisClkSig	sl
axisRstSig	sl
sAxisMasterSig	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlaveSig	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mAxisMasterSig	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlaveSig	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
axilClkSig	sl
axilRstSig	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_s_axis	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_m_axis	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	FirFilterMultiChannel <Entity FirFilterMultiChannel>

The documentation for this design unit was generated from the following file:

Signals

Instantiations