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SURF
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Inheritance diagram for FirFilterMultiChannelTestWrapper:
Collaboration diagram for FirFilterMultiChannelTestWrapper:Entities | |
| FirFilterMultiChannelTestWrapper.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
Ports | ||
| S_AXIS_ACLK | in | std_logic |
| S_AXIS_ARESETN | in | std_logic |
| S_AXIS_TVALID | in | std_logic |
| S_AXIS_TDATA | in | std_logic_vector ( 15 downto 0 ) |
| S_AXIS_TSTRB | in | std_logic_vector ( 1 downto 0 ) |
| S_AXIS_TKEEP | in | std_logic_vector ( 1 downto 0 ) |
| S_AXIS_TLAST | in | std_logic |
| S_AXIS_TDEST | in | std_logic_vector ( 0 downto 0 ) |
| S_AXIS_TID | in | std_logic_vector ( 0 downto 0 ) |
| S_AXIS_TUSER | in | std_logic_vector ( 0 downto 0 ) |
| S_AXIS_TREADY | out | std_logic |
| M_AXIS_ACLK | in | std_logic |
| M_AXIS_ARESETN | in | std_logic |
| M_AXIS_TVALID | out | std_logic |
| M_AXIS_TDATA | out | std_logic_vector ( 15 downto 0 ) |
| M_AXIS_TSTRB | out | std_logic_vector ( 1 downto 0 ) |
| M_AXIS_TKEEP | out | std_logic_vector ( 1 downto 0 ) |
| M_AXIS_TLAST | out | std_logic |
| M_AXIS_TDEST | out | std_logic_vector ( 0 downto 0 ) |
| M_AXIS_TID | out | std_logic_vector ( 0 downto 0 ) |
| M_AXIS_TUSER | out | std_logic_vector ( 0 downto 0 ) |
| M_AXIS_TREADY | in | std_logic |
| S_AXI_ACLK | in | std_logic |
| S_AXI_ARESETN | in | std_logic |
| S_AXI_AWADDR | in | std_logic_vector ( 3 downto 0 ) |
| S_AXI_AWPROT | in | std_logic_vector ( 2 downto 0 ) |
| S_AXI_AWVALID | in | std_logic |
| S_AXI_AWREADY | out | std_logic |
| S_AXI_WDATA | in | std_logic_vector ( 31 downto 0 ) |
| S_AXI_WSTRB | in | std_logic_vector ( 3 downto 0 ) |
| S_AXI_WVALID | in | std_logic |
| S_AXI_WREADY | out | std_logic |
| S_AXI_BRESP | out | std_logic_vector ( 1 downto 0 ) |
| S_AXI_BVALID | out | std_logic |
| S_AXI_BREADY | in | std_logic |
| S_AXI_ARADDR | in | std_logic_vector ( 3 downto 0 ) |
| S_AXI_ARPROT | in | std_logic_vector ( 2 downto 0 ) |
| S_AXI_ARVALID | in | std_logic |
| S_AXI_ARREADY | out | std_logic |
| S_AXI_RDATA | out | std_logic_vector ( 31 downto 0 ) |
| S_AXI_RRESP | out | std_logic_vector ( 1 downto 0 ) |
| S_AXI_RVALID | out | std_logic |
| S_AXI_RREADY | in | std_logic |